Abstract: An aluminum borate whisker reinforced and toughened non-metallic matrix composite is provided, which specifically includes a non-metallic material reinforced and toughened with aluminum borate whiskers. The composite exhibits a higher bending strength and fracture toughness and a higher wear resistance. A method for preparing the composite is also provided. The method includes mixing the aluminum borate whiskers and the non-metallic material to form a mixture; and sintering the mixture by a vacuum hot press method, or molding the mixture.

Abstract: A system including a processor, a memory controller, and a flash memory module. The processor is configured to generate a request to retrieve information corresponding to an address. The memory controller module includes a cache memory configured to store information, and a cache control logic module configured to determine whether the cache memory stores the information corresponding to the address, if the cache memory stores the information corresponding to the address, retrieve the information from the cache memory and provide the information to the processor, and if the cache memory does not store the information corresponding to the address, generate a flash memory read request based on the address. The flash memory module is configured to, in response to receiving the flash memory read request, provide the information corresponding to the address to the memory controller module.

Abstract: A circuit including a clock module, a control module, a manipulation module, and a function module. The clock module generates a first clock signal. The control module generates a control signal. The manipulation module, based on the control signal, either (i) forwards the first clock signal without modifying the first clock signal or (ii) modifies a cycle of the first clock signal to simulate a second clock signal. The second clock signal has a frequency higher than a frequency of the first clock signal. The function module: during a first mode and based on a non-modified cycle of the first clock signal, operates devices in a predetermined configuration; ceases operating in the first mode and changes the predetermined configuration of the devices to form a scan chain; and during a second mode and based on the modified cycle, operates the scan chain to test the devices.

Abstract: A system includes a programmable interface module located on an integrated circuit (IC), the programmable interface module configured to be programmed to operate in a plurality of modes, and communicate with at least one device external to the IC based on a selected one of the plurality of modes. Each of the plurality of modes corresponds to at least one of a type of peripheral feature, a type of communication interface, and a protocol type. An interface configuration module is configured to receive an indication of the selected one of the plurality of modes and program the programmable interface module to operate in the selected one of the plurality of modes in response to the indication.

Abstract: Apparatus having corresponding methods and computer-readable media comprise a function module to operate according to a clock signal; a clock control module to provide a clock gate signal; and a clock gate module to provide the clock signal to the function module only until the clock control module provides the clock gate signal; wherein the function module includes a plurality of storage elements, wherein the storage elements form a scan chain in response to a mode signal; and wherein the scan chain is configured to shift data stored therein out of the scan chain.

Abstract: Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus includes a digital electronic component configured to produce a clock signal. A first counter is configured to output a first count signal based on the clock signal and a second counter is configured to output a second count signal based on the clock signal. A power on reset logic is configured to provide a power on reset signal based on the first count signal and the second count signal, where the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power.

Abstract: Apparatus having corresponding methods and non-transitory computer-readable media comprise: a function module to operate according to a clock signal; a clock manipulation module to manipulate an edge of the clock signal responsive to occurrence of a predetermined condition; and a report module to indicate a clock cycle number of the edge of the clock signal responsive to occurrence of an error in the function module.

Abstract: Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed.

Abstract: Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus is implemented with a digital electronic component that produces a clock signal. The apparatus also includes a first counter that outputs a first count signal based on the clock signal and a second counter that outputs a second count signal based on the clock signal. The apparatus also includes a power on reset logic that selectively provides a power on reset signal based on the first count signal and the second count signal. The power on reset logic can also selectively disable the apparatus upon providing the power on reset signal.

Abstract: Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed.

Abstract: Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed.

Abstract: A method for testing a programmable logic device having defined programmable function blocks with programmable interconnects follows steps of (a) configuring, by programming, two or more similar groups of the function blocks and interconnects into identical state machines; (b) operating the programmed state machines by clock and reset signals to generate individual original signatures on global interconnect lines; and (c) comparing the original signatures of the two or more state machines for fault detection. Original signatures from different programmed groups of function blocks and interconnects at different dedicated test output blocks are compressed and passed to signature analysis circuitry where a final signature is analyzed as in indicator of faults. A microcontroller is taught for configuring and performing tests.