Abstract: In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. Doped source/drain regions are formed within semiconductive material laterally proximate the gate. Substantially amorphous insulating material is formed over and laterally proximate the gate. The substrate is provided within a chemical vapor deposition reactor.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric region, and the polysilicon is formed into a second capacitor electrode.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one-step process or a two-step process. In the one-step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two-step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and forming a catalyst material over the nitride layer, can be performed before annealing to form a catalyst body.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract: Fabrication techniques for making a semiconductor device. More specifically, techniques for fabricating a wordline in a memory device are provided. Specific heat treatments may be added to the process flow to remove or weaken certain layers formed in the wordlines. For instance, an SiNx layer and a crystallized W2N layer may form during the fabrication of the wordline. While the layers may provide certain advantages at certain points in the fabrication process, they may be undesirable at subsequent points. One or more anneal processes may be implemented at various points in the processing to eliminate the crystallized W2N layer and weaken the SiNx layer.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: An emission site for a large area passive matrix cold cathode field emission display having an emission tip with a sharp profile is disclosed. A metallic film formed of iridium silicide (IrSi) is used to coat the tip. By using IrSi the tips of the emission sites can be formed at low temperatures. In addition, IrSi is a fine grain material that maintains a sharp profile and can be formed in a layer as thin as 100 A°.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base, that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract: The invention includes a method of forming a semiconductor construction. A metal-rich metal suicide layer is formed on a silicon-comprising substrate, and a metal nitride layer is formed on the metal-rich metal silicide layer. The metal-rich metal silicide layer and metal nitride layer are thermally processed to convert some of the metal-rich metal silicide into a stoichiometric metal silicide region. The thermal processing also drives nitrogen from the metal nitride layer into the metal-rich metal silicide layer to convert some of the metal-rich metal silicide layer into a region comprising metal, silicon and nitrogen. The invention also includes semiconductor constructions comprising a layer of MSi2 and a layer of MSiqNr, where M is Ta, W or Mo, and both q and r are greater than 0 and less than 2.

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.