Abstract: Dynamically overriding a function based on a capability set. A computer system reads a portion of an executable image file. The portion includes a first memory address corresponding to a first callee function implementation. The first memory address was inserted into the portion by a compiler toolchain. Based on extensible metadata included in the executable image file, and based on a capability set that is specific to the computer system, the computer system determines a second memory address corresponding to a second callee function implementation. Before execution of the portion, the computer system modifies the portion to replace the first memory address with the second memory address.

Abstract: Dynamically overriding a function based on a capability set. A computer system reads a portion of an executable image file. The portion includes a first memory address corresponding to a first callee function implementation. The first memory address was inserted into the portion by a compiler toolchain. Based on extensible metadata included in the executable image file, and based on a capability set that is specific to the computer system, the computer system determines a second memory address corresponding to a second callee function implementation. Before execution of the portion, the computer system modifies the portion to replace the first memory address with the second memory address.

Abstract: Provided are dynamic region division and region passage identification methods and a cleaning robot. The dynamic region division method includes: acquiring environment information collected by a robot when working in a first region; determining whether the robot has completed a work task in the first region, when a presence of a passage entering a second region is determined based on the environment information; and complementing a boundary at the passage to block the passage, when the work task is not completed. According to the technical solution provided by the embodiment of the present application, the occurrence probability of repeated sweeping and miss sweeping is reduced, and the cleaning efficiency is high. In addition, the technical solution provided by the embodiment of the present application relies on the environment information collected during the work, rather than relying on historical map data, so that the environmental adaptability is high.

Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.

Abstract: Using a common reference address when processing calls among a native ABI and a foreign ABI. Based on caller calling using a reference address, a lookup structure is used to determine whether the reference address is within a memory range storing native code (and that the callee is native) or a memory range not storing native code (and that the callee is foreign). Execution of the callee is initiated based on one of (i) when the caller is native and when the callee is foreign, calling the callee using the reference address within an emulator; (ii) when the caller is foreign and the callee is native, calling an entry thunk; (iii) when the caller is native and the callee is foreign, calling an exit thunk; or (iv) when the caller is native and the callee is native, directly calling the callee using the reference address.

Abstract: A hybrid binary executable under both native processes and compatibility (e.g., emulated) processes. When the hybrid binary is loaded by a native process, the process executes a native code stream contained in the binary directly on a processor. When the hybrid binary is loaded by a compatibility process, the process executes an emulation-compatible (EC) code stream directly on a processor. When executing in a compatibility process, the EC code stream can interact with a foreign code stream that executes in an emulator. The foreign code stream can be included in the hybrid binary itself, or can be external to the hybrid binary. The hybrid binary format supports folding of code between the native code stream and the EC code stream. The hybrid binary comprises a set of memory transformations which are applied to image data obtained from the binary when the hybrid binary executes under the compatibility process.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: The present disclosure relates to audio processing methods and terminal devices. One example method includes determining, by a terminal device, an actual uplink gain based on a position relationship between an acoustic source and a microphone of the terminal device, and processing, by the terminal device, an audio signal from the acoustic source based on the actual uplink gain.

Abstract: Provided are dynamic region division and region passage identification methods and a cleaning robot. The dynamic region division method includes: acquiring environment information collected by a robot when working in a first region; determining whether the robot has completed a work task in the first region, when a presence of a passage entering a second region is determined based on the environment information; and complementing a boundary at the passage to block the passage, when the work task is not completed. According to the technical solution provided by the embodiment of the present application, the occurrence probability of repeated sweeping and miss sweeping is reduced, and the cleaning efficiency is high. In addition, the technical solution provided by the embodiment of the present application relies on the environment information collected during the work, rather than relying on historical map data, so that the environmental adaptability is high.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: The present disclosure relates to audio processing methods and terminal devices. One example method includes determining, by a terminal device, an actual uplink gain based on a position relationship between an acoustic source and a microphone of the terminal device, and processing, by the terminal device, an audio signal from the acoustic source based on the actual uplink gain.

Abstract: The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.

Abstract: Embodiments are directed to tracking variable location information in optimized code and efficiently collecting and storing reaching definition information. A computer system receives a portion of source code at a compiler, where the compiler is configured to compile and optimize the source code for execution. The computer system tags selected variables in the source code with a tag, where the tag is configured to provide location information for the variable. The computer system optimizes the received portion of source code including changing at least one of the tagged variables. The computer system also tracks the tagged variables as the variables are changed by the compiler during code optimization and persists the variable location information, so that the persisted variable location information is available to other compiler components.

Abstract: The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.

Abstract: Embodiments are directed to tracking variable location information in optimized code and efficiently collecting and storing reaching definition information. A computer system receives a portion of source code at a compiler, where the compiler is configured to compile and optimize the source code for execution. The computer system tags selected variables in the source code with a tag, where the tag is configured to provide location information for the variable. The computer system optimizes the received portion of source code including changing at least one of the tagged variables. The computer system also tracks the tagged variables as the variables are changed by the compiler during code optimization and persists the variable location information, so that the persisted variable location information is available to other compiler components.