Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to the first distance and being spaced apart from an adjacent unit by a second distance equal to the first width, forming a spacer conformally covering the first and second units, the spacer having a first thickness and being merged between the second units, removing a portion of the spacer on upper surfaces of the first and second units, and etching the mask in a region from which first and second units have been removed.

Abstract: A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip regions. The semiconductor device additionally includes a first optical measurement pattern disposed on the substrate. The semiconductor device further includes a second optical measurement pattern disposed on an upper layer of the first optical measurement pattern, the second optical measurement pattern being spaced apart from the first optical measurement pattern. The semiconductor device additionally includes a three-dimensional (3D) shielding structure surrounding the first optical measurement pattern and including an electrically conductive material.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip regions. The semiconductor device additionally includes a first optical measurement pattern disposed on the substrate. The semiconductor device further includes a second optical measurement pattern disposed on an upper layer of the first optical measurement pattern, the second optical measurement pattern being spaced apart from the first optical measurement pattern. The semiconductor device additionally includes a three-dimensional (3D) shielding structure surrounding the first optical measurement pattern and including an electrically conductive material.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: A method of forming a pattern of a semiconductor device includes forming a mask and a sacrificial layer on a substrate, etching the sacrificial layer in a first area of the substrate to form first units, each having a first width and a first distance from an adjacent unit, etching the sacrificial layer in a second area of the substrate to form second units, each having a second width equal to the first distance and being spaced apart from an adjacent unit by a second distance equal to the first width, forming a spacer conformally covering the first and second units, the spacer having a first thickness and being merged between the second units, removing a portion of the spacer on upper surfaces of the first and second units, and etching the mask in a region from which first and second units have been removed.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.

Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region.

Abstract: A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.

Abstract: In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

Abstract: A mask for forming patterns of a semiconductor device is provided. The mask includes first and second main patterns disposed to be spaced apart from each other about a cross point and extending in first and second directions different from each other, a third main pattern disposed spaced apart from the first and second main patterns while being disposed between the first and second main patterns so as to overlap the cross point, and at least one auxiliary pattern spaced apart from the third main pattern in the periphery of a portion of the third main pattern, which is not adjacent with the first and second main patterns.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

Abstract: In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

Abstract: A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower electrodes are disposed in a plurality of rows each extending in a first direction. A dielectric layer is disposed on the lower electrodes, and an upper electrode is disposed on the dielectric layer. The supports are in the form of stripes extending longitudinally in the first direction and spaced from each other along a second direction. Each of the supports engages the lower electrodes of a respective plurality of adjacent rows of the lower electrodes. Each one of the supports is also disposed at a different level in the device from the support that is adjacent thereto in the second direction.

Abstract: A mask for forming patterns of a semiconductor device is provided. The mask includes first and second main patterns disposed to be spaced apart from each other about a cross point and extending in first and second directions different from each other, a third main pattern disposed spaced apart from the first and second main patterns while being disposed between the first and second main patterns so as to overlap the cross point, and at least one auxiliary pattern spaced apart from the third main pattern in the periphery of a portion of the third main pattern, which is not adjacent with the first and second main patterns.

Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.