Abstract: Present techniques involve systems and methods for driving a synchronous bus by implementing repeaters along the bus to restore and/or amplify a signal transmitted through the bus. In one embodiment, a repeater may be implemented at different sections of a synchronous bus, and each repeater may be activated according to where a signal is to be transmitted. In another embodiment, decoders may be configured to each repeater on the synchronous bus. As a signal directed to a section of a bus is transmitted through the bus, each sequential decoder may identify the bus section to which a signal is directed. The decoder may enable its corresponding repeater based on the bus section to which the signal is directed, such that all repeaters along the bus which come before the signal destination may be enabled to allow signal transmission through the bus and signal restoration by the repeaters.

Abstract: Techniques for operating a touchscreen display are disclosed herein. In one embodiment, the touchscreen display device includes power regulation circuitry that supplies a first set of voltages to a display panel using high and low supply rails during a display period. During the blanking period following the display period, the high and low supply rails may be adjusted to a second set of voltages that provide for proper operation of touch-sensitive elements in the touchscreen display. Following the end of the blanking period, a portion of charge from the low supply rail is recycled by transferring the charge from the low supply rail back to the high supply rail to bring the high and low supply rails back to the first set of voltages for the next display period.

Abstract: Visual artifacts in a display are reduced by moving, to the extent possible, display driver components to the display surface itself, thereby shortening conductor distances and reducing the parasitic effects caused by parasitic resistance of the conductors between the display power supply and the display, and between the stabilizing capacitors and the display. To avoid interference with the device housing, low-profile driver components, including either or both of stabilizing capacitors and power supply terminals, can be provided and bonded to the surface of the display side of the outer layer of the display. Alternatively, the stabilizing capacitors can be formed on the display side in the same way that, e.g., in an LCD display, the transparent electrodes for controlling the liquid crystals are formed.

Abstract: A technique for reducing the kickback voltage error between two or more common voltage signal lines in a display device is provided. The kickback voltage error may be caused by driving a first and second common voltage at different levels. In one embodiment, a common voltage offset may be applied to the second common voltage such that the magnitude of the voltage kickback error is approximately equalized at the maximum and minimum pixel voltages for pixels coupled to the second common voltage. A data voltage offset, which may be determined based upon gray level data, may be applied to the data voltage supplied to the pixels coupled to the second common voltage. The foregoing technique may compensate for the kickback voltage error between the first and second common voltage lines, thereby reducing visual artifacts and improving color accuracy of the display.

Abstract: An electronic device is disclosed. In some embodiments, the electronic device includes a liquid-crystal display (LCD) and a plurality of driver integrated circuits (ICs) coupled to the LCD. The driver ICs may be disposed near non-central locations along a side of the LCD, and in some embodiments, one of the driver ICs may be a master driver IC and the other driver IC or driver ICs may be slave driver ICs.

Abstract: The same testing equipment can be used to test devices operating under different protocols. Where the testing protocol is slower than the native serial protocol of the high-speed serial link connecting the device processor to the component to be tested, the link may be adapted to carry the lower speed testing protocol. This may be accomplished by adding low-speed buffers to the circuits of the serial link, or the serial link may have a native low-speed protocol in addition to its high-speed protocol connections may be made to the pathways for the native low-speed protocol, or the testing protocol may be impressed on top of native low-speed protocol. Where the driver of the device being tested has limited number of pins, the test mode can be controlled by applying power to different power supply input pins.

Abstract: An electronic device is disclosed. In some embodiments, the electronic device includes a liquid-crystal display (LCD) and a plurality of driver integrated circuits (ICs) coupled to the LCD. The driver ICs may be disposed near non-central locations along a side of the LCD, and in some embodiments, one of the driver ICs may be a master driver IC and the other driver IC or driver ICs may be slave driver ICs.

Abstract: Techniques for controlling the slew rate of a signal independently of RC time constants are disclosed. In one embodiment, a gate driver circuit for an LCD panel may include a rail-to-rail operational amplifier having an output stage configured to produce a gate activation signal for switching pixels of the LCD panel. A slew rate control circuit may be provided for adjusting the slew rate of the gate activation signal by varying a bias current of the output stage relative to a compensation capacitance and a gain of the operational amplifier. For instance, the slew rate may be increased by increasing the bias current, and decreased by decreasing the bias current without the need to adjust RC variables.

Abstract: Present techniques involve methods and systems of inversion patterns for pixels in a display. Inversion techniques involve driving image signals having a first polarity to data lines of a pixel matrix during a first time period and driving image signals having an opposite polarity to the data lines during a second time period. In some embodiments, the pixels may be configured to have electrodes having only two finger electrodes, thus widening the distance between electrodes and decreasing the susceptibility for crosstalk between pixels. In some embodiments, horizontal cross-talk of electromagnetic fields between pixels may be further reduced by configuring the data line driving scheme such that voltage polarity is flipped for the pixels along every two, three, or more data line columns. Furthermore, a Z inversion pattern may be employed to reduce the occurrence of undesirable display artifacts.

Abstract: Systems, methods, and devices for efficient brightness control for an organic light emitting diode (OLED) display are provided. In one embodiment, such a method may include receiving image data into a data driver of an organic light emitting diode display and transforming the image data into a logarithmic domain. A dimming control value may be subtracted from this log-encoded image data. The resulting log-encoded dimmed image data may represent a darker version of the originally received image data. Thereafter, a pixel of the organic light emitting diode display may be driven based at least in part on the dimmed image data.

Abstract: Present techniques involve systems and methods for driving a synchronous bus by implementing repeaters along the bus to restore and/or amplify a signal transmitted through the bus. In one embodiment, a repeater may be implemented at different sections of a synchronous bus, and each repeater may be activated according to where a signal is to be transmitted. In another embodiment, decoders may be configured to each repeater on the synchronous bus. As a signal directed to a section of a bus is transmitted through the bus, each sequential decoder may identify the bus section to which a signal is directed. The decoder may enable its corresponding repeater based on the bus section to which the signal is directed, such that all repeaters along the bus which come before the signal destination may be enabled to allow signal transmission through the bus and signal restoration by the repeaters.

Abstract: A responsive, low-power display panel power supply is provided. In one embodiment, such a display panel power supply may include a regulator whose responsiveness varies depending on the bias current it consumes, and a current source that provides a variable bias current. The regulator may provide the display panel a supply voltage and a supply current based on a reference voltage and a bias current. Various events taking place in the display panel, such as toggling at COM lines, source lines, and/or gate lines may cause parasitic capacitances within the display panel to draw more or less supply current. To ensure the regulator remains suitably responsive to such changes in supply current, while reducing the total power consumed by the power supply, the current source may provide a higher bias current to the regulator at least while the supply current is changing than at certain other times.

Abstract: A display device having a data voltage generation circuit and a common voltage generation circuit that are both coupled to a common reference voltage is provided. By utilizing a common ground, variations between the data signals relative to the common voltage may be reduced, thereby improving voltage precision and color accuracy. In one embodiment, the data voltage generation circuit may be a gamma adjustment circuit that utilizes a resistor string having a center grounding point. The common voltage generation circuit may share the resistor string and the grounding point with the gamma adjustment circuit. Thus, data voltage signals and common voltage signals may be derived based on the same voltage reference point. Further, by sharing the resistor string, the total number of circuit components in the display device may be reduced, thereby reducing overall chip area and/or manufacturing costs.

Abstract: Systems and methods of the present disclosure relates generally to techniques for controlling a gate signal applied to a transistor in an electronic component. One embodiment includes decreasing a skew rate at the rising and/or falling edges of the gate signal to reduce the effects of data signal errors. Decreasing the gate signal falling edge skew rate may decrease clock feedthrough effects of the transistor, and decreasing the gate signal rising edge skew rate may decrease crosstalk effects between more than one data paths in the electronic component. The falling edge skew rate may be manipulated by initially increasing the activating voltage of the gate signal to a higher voltage, such that the gate signal may take longer to fall. The rising edge skew rate may be manipulated by increasing a voltage later during the activating period, such that the gate signal may take longer to rise.

Abstract: A technique for reducing the kickback voltage error between two or more common voltage signal lines in a display device is provided. The kickback voltage error may be caused by driving a first and second common voltage at different levels. In one embodiment, a common voltage offset may be applied to the second common voltage such that the magnitude of the voltage kickback error is approximately equalized at the maximum and minimum pixel voltages for pixels coupled to the second common voltage. A data voltage offset, which may be determined based upon gray level data, may be applied to the data voltage supplied to the pixels coupled to the second common voltage. The foregoing technique may compensate for the kickback voltage error between the first and second common voltage lines, thereby reducing visual artifacts and improving color accuracy of the display.

Abstract: Techniques are provided for synchronizing the data signals transmitted through a synchronous bus in a display device. One embodiment includes manipulating the clock signals and/or data signals transmitted by a display controller in the display based on the location on the bus where a data signal is to be transmitted. For example, a pre-emphasized clock signal having a higher initial voltage level may be used for a data signal transmitted farther on the bus from the display controller. The pre-emphasized clock signal may compensate for propagation delays associated with transmitting the data signal through the bus. Further, a de-emphasized clock signal may be used for data signals transmitted to a section on the bus closer on to the display controller, and neutral clock signals may be used for data signals transmitted to a section that is of intermediate distance from the display controller.

Abstract: A display configured to reduce intra-pixel crosstalk is provided. In one embodiment, a system includes a processor, a memory, and a display. The display may include a pixel array and associated driving circuitry. The display may be configured to balance charges induced on a gate line and on an adjacent common line of the pixel array in response to application of a first data voltage on a first data line, and to perform such balancing before applying a second data voltage to a second data line adjacent the first data line to reduce or eliminate intra-pixel crosstalk. Additional systems, devices, and methods relating to reducing intra-pixel crosstalk in a display are also disclosed.

Abstract: Methods and apparatus are provided for generating low EMI display driver power supply. The methods and apparatus include switching circuits that utilize two groups of parallel circuit traces, each of which is coupled to one end of a switching device. The two groups of traces are configured to be interleaved with each other such that no two traces from either group are next to any other traces from the same group. When the switching device is activated, current flows through the circuit and charges an energy storage element. When the switching device is deactivated, the energy storage element discharges a portion of its energy to a second energy storage element and to the driver circuits. In another embodiment, an additional circuit trace is provided which is only connected on one end and is free floating on the other end to capture the majority of EMI remaining that was generated by the switching circuit.

Abstract: Systems and methods are disclosed for various inversion techniques for an LCD array, such as a staggered 2-line inversion, a staggered 1-line inversion, or a staggered N-line inversion. The staggered inversion may invert 2-lines, 1-line or N-lines of an array over the duration of a frame displayed on the array. Additional systems and methods may include a high impedance power reduction technique that may be applied alone or in combination with the various inversion techniques. Specifically, electrode drivers for “idle” lines of a staggered 1-line, 2-line, or N-line inversion may be switched to a high impedance state such that the corresponding drivers for the idle lines use reduced power during the inversion of the “active” lines.

Abstract: Methods and apparatus are provided for generating low EMI display driver power supply. The methods and apparatus include switching circuits that utilize two groups of parallel circuit traces, each of which is coupled to one end of a switching device. The two groups of traces are configured to be interleaved with each other such that no two traces from either group are next to any other traces from the same group. When the switching device is activated, current flows through the circuit and charges an energy storage element. When the switching device is deactivated, the energy storage element discharges a portion of its energy to a second energy storage element and to the driver circuits. In another embodiment, an additional circuit trace is provided which is only connected on one end and is free floating on the other end to capture the majority of EMI remaining that was generated by the switching circuit.