Patents by Inventor Yong-Moon Jang

Yong-Moon Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720491
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Won Chul Lee, Sung Yeon Kim, Jae Hong Park, Chan Hoon Park, Yong Moon Jang, Je Woo Han
  • Patent number: 10607855
    Abstract: A method for fabricating a semiconductor device includes forming an insulating layer on a substrate; forming a first mask pattern including silicon on the insulating layer and forming a second mask pattern including an oxide on the first mask pattern; forming a coating layer that includes carbon and which covers an upper surface of the insulating layer, a sidewall of the first mask pattern, and the second mask pattern; removing a portion of the coating layer and the second mask pattern; forming a metal layer on an upper surface of the first mask pattern and on a sidewall of the coating layer; exposing the upper surface of the insulating layer by removing the coating layer; and etching the insulating layer by using the first mask pattern and the metal layer as a mask.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: March 31, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Ho Yoon, Jae Hong Park, Da Il Eom, Sung Yeon Kim, Jin Young Park, Yong Moon Jang
  • Publication number: 20190273130
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 5, 2019
    Inventors: Jun Ho YOON, Won Chul LEE, Sung Yeon KIM, Jae Hong PARK, Chan Hoon PARK, Yong Moon JANG, Je Woo HAN
  • Patent number: 10319805
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ho Yoon, Won Chul Lee, Sung Yeon Kim, Jae Hong Park, Chan Hoon Park, Yong Moon Jang, Je Woo Han
  • Publication number: 20190027376
    Abstract: A method for fabricating a semiconductor device includes forming an insulating layer on a substrate; forming a first mask pattern including silicon on the insulating layer and forming a second mask pattern including an oxide on the first mask pattern; forming a coating layer that includes carbon and which covers an upper surface of the insulating layer, a sidewall of the first mask pattern, and the second mask pattern; removing a portion of the coating layer and the second mask pattern; forming a metal layer on an upper surface of the first mask pattern and on a sidewall of the coating layer; exposing the upper surface of the insulating layer by removing the coating layer; and etching the insulating layer by using the first mask pattern and the metal layer as a mask.
    Type: Application
    Filed: January 4, 2018
    Publication date: January 24, 2019
    Inventors: JUN HO YOON, Jae Hong Park, DA IL EOM, Sung Yeon Kim, Jin Young Park, Yong Moon Jang
  • Patent number: 10062550
    Abstract: Provided are substrate processing apparatuses including a temperature measurement unit. The substrate processing apparatus comprises a chamber including a substrate processing region, a dielectric sheet that is disposed on the substrate processing region and includes an insertion hole and a temperature measurement unit that is disposed on the dielectric sheet to measure the temperature of the dielectric sheet, and has a screw portion inserted into the insertion hole, wherein each of the insertion hole and the screw portion has thread helixes meshed with each other.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Pyo Hong, Kwang-Nam Kim, Sang-Dong Kwon, Jong-Woo Sun, Sang-Rok Oh, Yong-Moon Jang
  • Publication number: 20180108728
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an oxide film on a target layer, forming a first mask film on the oxide film, wherein the first mask film contains a semiconductor material and has a first thickness and a first etch selectivity with respect to the oxide film, forming a second mask film on the first mask film, wherein the second mask film contains a metal and has a second thickness smaller than the first thickness and a second etch selectivity larger than the first etch selectivity with respect to the oxide film, forming a second mask film pattern by patterning the second mask film, forming a first mask film pattern by patterning the first mask film, etching some portions of the oxide film by using the second mask film pattern as an etch mask film, and etching the rest of the oxide film by using the first mask film pattern as an etch mask film to form a hole, wherein the target layer is exposed via the hole.
    Type: Application
    Filed: June 19, 2017
    Publication date: April 19, 2018
    Inventors: Jun Ho YOON, Won Chul LEE, Sung Yeon KIM, Jae Hong PARK, Chan Hoon PARK, Yong Moon JANG, Je Woo HAN
  • Publication number: 20170062245
    Abstract: Provided are substrate processing apparatuses including a temperature measurement unit. The substrate processing apparatus comprises a chamber including a substrate processing region, a dielectric sheet that is disposed on the substrate processing region and includes an insertion hole and a temperature measurement unit that is disposed on the dielectric sheet to measure the temperature of the dielectric sheet, and has a screw portion inserted into the insertion hole, wherein each of the insertion hole and the screw portion has thread helixes meshed with each other.
    Type: Application
    Filed: April 29, 2016
    Publication date: March 2, 2017
    Inventors: Jung-Pyo Hong, Kwang-Nam KIM, Sang-Dong KWON, Jong-Woo SUN, Sang-Rok OH, Yong-Moon JANG
  • Patent number: 9230808
    Abstract: A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-woo Han, Jun-ho Yoon, Dong-chan Kim, Gyung-jin Min, Jae-hong Park, Yong-moon Jang
  • Patent number: 8815697
    Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Yoon, Bong-Jin Kuh, Ki-Chul Kim, Gyung-Jin Min, Tae-Jin Park, Sang-Ryol Yang, Jung-Min Oh, Sang-Yoon Woo, Young-Sub Yoo, Ji-Eun Lee, Jong-Sung Lim, Yong-Moon Jang, Han-Mei Choi, Je-Woo Han
  • Publication number: 20140038383
    Abstract: A method of fabricating a semiconductor device includes providing a substrate that is divided into a first region on which a pattern layer is formed and a second region on which a photo key is formed. A silicon layer is formed on the first region and second region of the substrate. The silicon layer is patterned to form a hole exposing a photo key portion of the second region on which the photo key is formed. A buried oxide layer is formed to fill the hole exposing the photo key portion. The silicon layer is patterned by using the photo key formed under the buried oxide layer to form a silicon pattern layer.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 6, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-woo HAN, Jun-ho YOON, Dong-chan KIM, Gyung-jin MIN, Jae-hong PARK, Yong-moon JANG
  • Publication number: 20130005110
    Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.
    Type: Application
    Filed: May 23, 2012
    Publication date: January 3, 2013
    Inventors: Jun-Ho Yoon, Bong-Jin Kuh, Ki-Chul Kim, Gyung-Jin Min, Tae-Jin Park, Sang-Ryol Yang, Jung-Min Oh, Sang-Yoon Woo, Young-Sub Yoo, Ji-Eun Lee, Jong-Sung Lim, Yong-Moon Jang, Han-Mei Choi, Je-Woo Han