Patents by Inventor YongQiang Xiong
YongQiang Xiong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12197367Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.Type: GrantFiled: June 29, 2023Date of Patent: January 14, 2025Inventors: Peng Cheng, Ran Shu, Guo Chen, Yongqiang Xiong, Jiansong Zhang, Ningyi Xu, Thomas Moscibroda
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Publication number: 20240333437Abstract: Some implementations relate to direct access to a storage device using a data plane of a switch. A response signal for a first packet transmitted from the switch to the storage device is received from a storage device. The first packet encapsulates a packet sequence number and first data to be transmitted by the switch. The response signal contains the packet sequence number. If the response signal is a negative acknowledgement response signal, a first state sequence number of the switch is updated with the packet sequence number contained in the response signal. The first state sequence number represents a sequence number of a packet to be transmitted by the switch. The first state sequence number and second data to be transmitted by the switch are encapsulated in a second packet to be transmitted to the storage device.Type: ApplicationFiled: July 22, 2022Publication date: October 3, 2024Inventors: Wenxue CHENG, Ziyuan LIU, Yongqiang XIONG, Zhixiong NIU, Peng CHENG, Lihua YUAN, Jacob NELSON, Dan PORTS
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Publication number: 20240240706Abstract: A fastening apparatus for connecting a thrust pad to a carrying member. The thrust pad is provided with a first recess and a communication hole communicating with the first recess. The carrying member is provided with a threaded hole. The aperture of the communication hole is greater than the aperture of the threaded hole. The fastening apparatus includes a bolt and a connection structure. An end cap of the bolt is disposed in the first recess. A screw of the bolt passes through the connection structure and is threaded into the threaded hole. The connection structure is able to be clamped between the end cap and the carrying member.Type: ApplicationFiled: December 26, 2023Publication date: July 18, 2024Inventors: Haifeng LUO, Yongqiang XIONG, Wenxiang DING, Zhongkui SUN, Hongjian LI, Hechao ZHANG
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Publication number: 20240169463Abstract: A computing system including a plurality of processing devices configured to execute a Mixture-of-Experts (MoE) layer included in an MoE model. The processing devices are configured to, in each of a plurality of iterations, at each of the processing devices, receive a respective plurality of input tokens. Executing the MoE layer further includes, at each of the processing devices, selecting one or more destination expert sub-models associated with the input tokens. Respective numbers k of expert sub-models selected differ across the iterations. At each of the processing devices, executing the MoE layer further includes conveying the input tokens to the one or more destination expert sub-models. Executing the MoE layer further includes generating one or more respective expert sub-model outputs at the one or more destination expert sub-models. Executing the MoE layer further includes generating and outputting an MoE layer output based on the one or more expert sub-model outputs.Type: ApplicationFiled: November 10, 2022Publication date: May 23, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Yifan XIONG, Changho HWANG, Wei CUI, Ziyue YANG, Ze LIU, Han HU, Zilong WANG, Rafael Omar SALAS, Jithin JOSE, Prabhat RAM, Ho-Yuen CHAU, Peng CHENG, Fan YANG, Mao YANG, Yongqiang XIONG
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Publication number: 20240160894Abstract: A computing system is provided, including a plurality of processing devices configured to execute a Mixture-of-Experts (MoE) layer included in an MoE model. The MoE layer includes a plurality of expert sub-models that each have a respective plurality of parameter values. The MoE layer is configured to be switchable between a data parallel mode and an expert-data-model parallel mode without conveying the respective parameter values of the expert sub-models among the plurality of processing devices.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Yifan XIONG, Changho HWANG, Wei CUI, Ziyue YANG, Ze LIU, Han HU, Zilong WANG, Rafael Omar SALAS, Jithin JOSE, Prabhat RAM, Ho-Yuen CHAU, Peng CHENG, Fan YANG, Mao YANG, Yongqiang XIONG
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Publication number: 20240160906Abstract: A computing system including a plurality of processing devices configured to execute a Mixture-of-Experts (MoE) layer included in an MoE model. The processing devices are configured to execute the MoE layer at least in part by, during a first collective communication phase between the processing devices, splitting each of a plurality of first input tensors along a first dimension to obtain first output tensors. Executing the MoE layer further includes processing the first output tensors at a respective a plurality of expert sub-models to obtain a plurality of second input tensors. Executing the MoE layer further includes, during a second collective communication phase between the processing devices, receiving the second input tensors from the expert sub-models and concatenating the second input tensors along the first dimension to obtain second output tensors. Executing the MoE layer further includes outputting the second output tensors as output of the MoE layer.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Yifan XIONG, Changho HWANG, Wei CUI, Ziyue YANG, Ze LIU, Han HU, Zilong WANG, Rafael Omar SALAS, Jithin JOSE, Prabhat RAM, Ho-Yuen CHAU, Peng CHENG, Fan YANG, Mao YANG, Yongqiang XIONG
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Patent number: 11934340Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.Type: GrantFiled: April 11, 2022Date of Patent: March 19, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Guo Chen, Thomas Moscibroda, Peng Cheng, Yuanwei Lu, Yongqiang Xiong
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Publication number: 20240086719Abstract: A computing system including a plurality of processing devices configured to execute a Mixture-of-Experts (MoE) layer. The processing devices are configured to execute the MoE layer at least in part by receiving an input tensor including input tokens. Executing the MoE layer further includes computing a gating function output vector based on the input tensor and computing a sparse encoding of the input tensor and the gating function output vector. The sparse encoding indicates one or more destination expert sub-models. Executing the MoE layer further includes dispatching the input tensor for processing at the one or more destination expert sub-models, and further includes computing an expert output tensor. Executing the MoE layer further includes computing an MoE layer output at least in part by computing a sparse decoding of the expert output tensor. Executing the MoE layer further includes conveying the MoE layer output to an additional computing process.Type: ApplicationFiled: May 16, 2023Publication date: March 14, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Yifan XIONG, Changho HWANG, Wei CUI, Ziyue YANG, Ze LIU, Han HU, Zilong WANG, Rafael Omar SALAS, Jithin JOSE, Prabhat RAM, Ho-Yuen CHAU, Peng CHENG, Fan YANG, Mao YANG, Yongqiang XIONG
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Publication number: 20230350825Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.Type: ApplicationFiled: June 29, 2023Publication date: November 2, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Peng CHENG, Ran SHU, Guo CHEN, Yongqiang XIONG, Jiansong ZHANG, Ningyi XU, Thomas MOSCIBRODA
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Patent number: 11726938Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.Type: GrantFiled: December 23, 2021Date of Patent: August 15, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Peng Cheng, Ran Shu, Guo Chen, Yongqiang Xiong, Jiansong Zhang, Ningyi Xu, Thomas Moscibroda
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Publication number: 20230079033Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AH traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.Type: ApplicationFiled: November 14, 2022Publication date: March 16, 2023Inventors: Yongqiang Xiong, Chih-Yung Wang, Jeongseok Son
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Patent number: 11503004Abstract: The present disclosure provides technical solutions related to distributed IPSec gateway. A control plane and a data plane of the IPSec gateway are divided, a plurality of gateway processing nodes may be run in the data plane to process data packets of incoming ESP/AR traffic and/or data packets of outgoing IP traffic. IKE information interaction may be handled in the control plane and the traffic may be steered on each gateway processing node in the data plane.Type: GrantFiled: May 1, 2018Date of Patent: November 15, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Yongqiang Xiong, Chih-Yung Wang, Jeongseok Son
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Patent number: 11463462Abstract: The present concepts relate to identifying entities based on their behavior using machine learning models. Where an entity may be a bot or a human, the entity's requests sent to a website are used to generate a graph. The graph may be used to create an image, such that the image reflects the entity's browsing behavior. A machine learning model, which has been trained using a first training set of images that correspond to bots and a second training set of images that correspond to humans, can determine whether the entity is a bot or a human by performing an image classification.Type: GrantFiled: June 17, 2019Date of Patent: October 4, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Yang Luo, Peng Cheng, Yongqiang Xiong, Qian Li
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Publication number: 20220309025Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.Type: ApplicationFiled: April 11, 2022Publication date: September 29, 2022Inventors: Guo Chen, Thomas Moscibroda, Peng Cheng, Yuanwei Lu, Yongqiang Xiong
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Publication number: 20220217098Abstract: In accordance with implementations of the subject matter described herein, there is provided a solution for streaming communication between devices. In this solution, a memory of a first device comprising a ring buffer is allocated to be dedicated for storing a data stream of an application to be transmitted to a second electronic device. The application of the first device writes data to be transmitted into the ring buffer, to form a portion of the first data stream, and a write pointer of the ring buffer is thus updated. A portion of data is read based on a source memory address from the ring buffer via the interface device. The interface device also transmits the data portion to a second device. The read data portion is stored in a dedicated ring buffer of the memory. In accordance with the solution, an efficient streaming communication interface is provided between devices.Type: ApplicationFiled: April 2, 2020Publication date: July 7, 2022Inventors: Zhixiong Niu, Ran Shu, Lei Qu, Peng Chen, Yongqiang Xiong, Guo Chen
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Publication number: 20220206979Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.Type: ApplicationFiled: December 23, 2021Publication date: June 30, 2022Applicant: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Peng CHENG, Ran SHU, Guo CHEN, Yongqiang XIONG, Jiansong ZHANG, Ningyi XU, Thomas MOSCIBRODA
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Patent number: 11308024Abstract: In accordance with implementations of the subject matter described herein, there provides a solution for multi-path RDMA transmission. In the solution, at least one packet is generated based on an RDMA message to be transmitted from a first device to a second device. The first device has an RDMA connection with the second device via a plurality of paths. A first packet in the at least one packet includes a plurality of fields, which include information for transmitting the first packet over a first path of the plurality of paths. The at least one packet is transmitted to the second device over the plurality of paths via an RDMA protocol. The first packet is transmitted over the first path. The multi-path RDMA transmission solution according to the subject matter described herein can efficiently utilize rich network paths while maintaining a low memory footprint in a network interface card.Type: GrantFiled: December 6, 2018Date of Patent: April 19, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Guo Chen, Thomas Moscibroda, Peng Cheng, Yuanwei Lu, Yongqiang Xiong
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Patent number: 11243901Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.Type: GrantFiled: April 24, 2018Date of Patent: February 8, 2022Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Peng Cheng, Ran Shu, Guo Chen, Yongqiang Xiong, Jiansong Zhang, Ningyi Xu, Thomas Moscibroda
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Patent number: 11042497Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.Type: GrantFiled: April 25, 2018Date of Patent: June 22, 2021Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Peng Cheng, Ran Shu, Guo Chen, Yongqiang Xiong, Jiansong Zhang, Ningyi Xu, Thomas Moscibroda
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Publication number: 20200396233Abstract: The present concepts relate to identifying entities based on their behavior using machine learning models. Where an entity may be a bot or a human, the entity's requests sent to a website are used to generate a graph. The graph may be used to create an image, such that the image reflects the entity's browsing behavior. A machine learning model, which has been trained using a first training set of images that correspond to bots and a second training set of images that correspond to humans, can determine whether the entity is a bot or a human by performing an image classification.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Applicant: Microsoft Technology Licensing, LLCInventors: Yang LUO, Peng CHENG, Yongqiang XIONG, Qian LI