Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.

Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to facilitate frequency locking of the SS-PLL.

Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.

Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.

Abstract: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.

Abstract: Power detectors with temperature compensation and having improved accuracy over temperature are disclosed. In an aspect of the disclosure, variations of a power detector gain over temperature is reduced by varying both the gate and drain voltages of MOS transistors within a power detector. In an exemplary design, an apparatus includes at least one MOS transistor, which receives an input signal, detects the power of the input signal based on a power detection gain, and provides an output signal indicative of the power of the input signal. The at least one MOS transistor is applied a variable gate bias voltage and a variable drain bias voltage in order to reduce variations of the power detection gain over temperature. At least one additional MOS transistor may receive a second variable gate bias voltage and provide the variable drain bias voltage for the at least one MOS transistor.

Abstract: An apparatus and method for an interface for transmitting high speed data between circuits. A driver circuit produces first and second differential currents from a digital signal that drive first and second transmission lines. A receiver is connected through first and second terminating resistors to said transmission lines. The resistive elements are in turn connected to first and second common base amplifiers where the differential currents are converted to a differential voltage. The input impedance to the first and second common-base amplifiers is further lowered by a differential amplifier having inputs connected to the inputs of the common-base amplifiers, and an output connected to the bases of said common-base amplifiers. As a result, voltage conversion of the differential signals takes place in the common-base amplifiers and not in the terminating resistors, reducing the level of the differential currents and permitting an increase in the digital data rate.

Abstract: An apparatus and method for an interface for transmitting high speed data between circuits. A driver circuit produces first and second differential currents from a digital signal that drive first and second transmission lines. A receiver is connected through first and second terminating resistors to said transmission lines. The resistive elements are in turn connected to first and second common base amplifiers where the differential currents are converted to a differential voltage. The input impedance to the first and second common-base amplifiers is further lowered by a differential amplifier having inputs connected to the inputs of the common-base amplifiers, and an output connected to the bases of said common-base amplifiers. As a result, voltage conversion of the differential signals takes place in the common-base amplifiers and not in the terminating resistors, reducing the level of the differential currents and permitting an increase in the digital data rate.