Abstract: A method to design parallel TH precoders and a circuit architecture to implement parallel TH precoders have been presented. The parallel design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The parallel design also relies on the fact that the compensation signal has finite levels. Therefore, precomputation techniques can be applied to calculate intermediate signal values for all possible values of the compensation signal.

Abstract: The invention relates to techniques for implementing high-speed precoders, such as Tomlinson-Harashima (TH) precoders. In one aspect of the invention, look-ahead techniques are utilized to pipeline a TH precoder, resulting in a high-speed TH precoder. These techniques may be applied to pipeline various types of TH precoders, such as Finite Impulse Response (FIR) precoders and Infinite Impulse Response (IIR) precoders. In another aspect of the invention, parallel processing multiple non-pipelined TH precoders results in a high-speed parallel TH precoder design. Utilization of high-speed TH precoders may enable network providers to for example, operate 10 Gigabit Ethernet with copper cable rather than fiber optic cable.

Abstract: The invention relates to techniques for pipelining parallel decision feedback decoders (PDFDs) for high speed communication systems, such as 10 Gigabit Ethernet over copper medium (10GBASE-T). In one aspect, the decoder applies look-ahead methods to two concurrent computation paths. In another aspect of the invention, retiming and reformulation techniques are applied to a parallel computation scheme of the decoder to remove all or a portion of a decision feedback unit (DFU) from a critical path of the computations of the pipelined decoder. In addition, the decoder may apply a pre-cancellation technique to a parallel computation scheme to remove the entire DFU from the critical path.

Abstract: Digital communications systems employ trellis coded modulation schemes. A K-dimensional trellis coded modulated symbol is transmitted over M channels in K/M cycles (where M divides K). K/M consecutive data units are transmitted serially in a time multiplexed manner in K/M consecutive cycles over one channel. If M=1, then each symbol is transmitted over one channel in K cycles in a time-multiplexed manner. At the receiver, a symbol is formed by grouping the data received from M channels in K/M cycles and this symbol is then decoded by a joint equalizer and decoder. If the number of parallel channels is N, then N/M trellis coded modulators and N/M decoders can be used in parallel. The advantage of this approach is an increase in speed by factor N/M.