Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A semiconductor device includes a substrate having a cell region, a boundary region, a peripheral region sequentially arranged in a first direction, an active pattern extending in the cell region in a second direction forming a first acute angle with respect to the first direction, and a boundary pattern in the cell region and directly adjacent to the boundary region. The boundary pattern includes a first side surface extending in the second direction and a first boundary surface extending in a third direction, which is perpendicular to the first direction, from the first side surface, and the first boundary surface defines a boundary between the cell region and the boundary region.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A semiconductor device includes a substrate having a cell region, a boundary region, a peripheral region sequentially arranged in a first direction, an active pattern extending in the cell region in a second direction forming a first acute angle with respect to the first direction, and a boundary pattern in the cell region and directly adjacent to the boundary region. The boundary pattern includes a first side surface extending in the second direction and a first boundary surface extending in a third direction, which is perpendicular to the first direction, from the first side surface, and the first boundary surface defines a boundary between the cell region and the boundary region.

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.

Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.

Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.

Abstract: A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.