Abstract: The present disclosure relates to semiconductor structures and, more particularly, to 3-contact hall sensors and methods of manufacture and modes of operation. The structure includes: a plurality of sensing blocks each of which include a plurality of contacts; a first switching element connecting to a first set of sensing blocks of the plurality of sensing blocks; and a second switching element connecting to a second set of sensing blocks of the plurality of sensing blocks.

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive select gate structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive select gate structure is shared by the first and second memory cells.

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells.

Abstract: A nonvolatile memory device is provided. The device comprises a floating gate having a first finger and a second finger and an active region below the floating gate fingers. A first doped region is in the active region laterally displaced from the first floating gate finger on a first side. A second doped region is in the active region laterally displaced from the first floating gate finger on a second side. A third doped region is in the active region laterally displaced from the second floating gate finger and the second doped region.

Abstract: A nonvolatile memory device is provided. The device comprises a memory transistor. A first capacitor is coupled to the memory transistor. A second capacitor is coupled to the memory transistor. The second capacitor comprises a first electrode and a second electrode. The first capacitor and the second capacitor are connected to separate input terminals.

Abstract: A memory device is provided. The memory device includes an active region in a substrate, an electrically-isolated electrode, and a dielectric layer. The electrically-isolated electrode is disposed over the active region. The dielectric layer is disposed between the electrically-isolated electrode and the active region and has a first dielectric portion having a first thickness and a second dielectric portion having a second thickness.

Abstract: A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells.

Abstract: A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.

Abstract: A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells.

Abstract: A device having a Hall effect sensor is provided. The Hall effect sensor includes a sensor well and a Hall plate disposed within the sensor well. The Hall plate includes a first current terminal and a second current terminal configured to flow a current through the Hall plate, and the Hall plate further includes a first sensing terminal and a second sensing terminal configured to sense a Hall voltage. A separation layer and a separation well are disposed within the sensor well, as well as surround the Hall plate and isolate the Hall plate. At least one of a current sensitivity and a resistance of the Hall effect sensor is tunable based on an adjustable thickness of the Hall plate. The thickness of the Hall plate is adjustable based at least in part on implants in the separation layer and/or a bias voltage applied to the separation layer.

Abstract: A device having a Hall effect sensor is provided. The Hall effect sensor includes a sensor well and a Hall plate disposed within the sensor well. The Hall plate includes a first current terminal and a second current terminal configured to flow a current through the Hall plate, and the Hall plate further includes a first sensing terminal and a second sensing terminal configured to sense a Hall voltage. A separation layer and a separation well are disposed within the sensor well, as well as surround the Hall plate and isolate the Hall plate. At least one of a current sensitivity and a resistance of the Hall effect sensor is tunable based on an adjustable thickness of the Hall plate. The thickness of the Hall plate is adjustable based at least in part on implants in the separation layer and/or a bias voltage applied to the separation layer.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.

Abstract: Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

Abstract: Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.

Abstract: Integrated circuit devices including vertical Hall elements and lateral Hall elements and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit device includes a substrate including a lateral element region and a vertical element region. The integrated circuit device includes a well in the lateral element region and in the vertical element region of the substrate. Further, the integrated circuit device includes an insulating layer disposed over the substrate in the lateral element region, a semiconductor-over-insulator (SOI) semiconductor layer disposed over the insulating layer in the lateral element region, and lateral element conductive taps located in the semiconductor layer, wherein a lateral Hall element is defined in the lateral element region. Also, the integrated circuit device includes vertical element taps located in the well in the vertical element region, wherein a vertical Hall element is defined in the vertical element region.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.

Abstract: An integrated Hall effect sensor is disclosed. The integrated Hall effect sensor has high tunable sensitivity by varying the thickness of the Hall plate. The Hall effect sensor is integrated onto a crystalline-on-insulator substrate, such as silicon-on-insulator (SOI) substrate. The Hall plate is part of the surface substrate of the SOI substrate. A sensor well is disposed in the bulk substrate of the SOI substrate. By applying an appropriate well bias voltage, the thickness of the Hall plate can be tuned from below the surface substrate to achieve the desired sensitivity. A gate may also be provided on the surface substrate. Biasing the gate with an appropriate gate bias voltage can further enhance thickness tunability of the Hall plate from above to achieve the desired sensitivity.