Abstract: A reprint apparatus may include: a defect checking unit configured to check a defective portion in a solder resist layer of a circuit board; a material filling unit positioned above the circuit board to fill the defective portion with a filling material; and a curing unit configured to cure the material filled in the defective portion. The defect checking unit may be configured to calculate a volume of the defective portion, and the material filling unit may be configured to calculate a discharge amount of the filling material based on the calculated volume of the defective portion, and then discharge the filling material by the discharge amount.

Abstract: A multilevel processing in memory (PIM) includes a processor in which an optimal operator installed at several layers of memory, an accelerator type circuit for processing an irregular operation, and a scheduler for processing an irregular operation have been installed. The multilevel processing in memory includes a memory module including at least one rank in which a computation operation and a data storage operation are performed in response to a control command from a memory controller. The memory module, the rank, a PIM command scheduler included in the rank, a bank group processing unit, and a bank group constitute a plurality of layers, respectively.

Abstract: Disclosed are oxadiazole compounds and pharmaceutically acceptable salts thereof. The compounds and pharmaceutically acceptable salts thereof are specifically suitable for the treatment of neurological diseases such as epilepsy.

Abstract: A battery module includes a sub module including a plurality of battery cells, a lower housing to receive the sub module therein and having an opening, a first housing cover coupled to the lower housing, covering the opening of the lower housing, and having a gas inlet, a second housing cover coupled to the first housing cover from above to form a gas receiving space therebetween, and having a gas outlet, and a variable partition structure using hinges installed in the gas receiving space to partition the gas receiving space to define a gas exhaust path to increase a movement path of a flame entering together with gas occurred in the sub module and entering the gas receiving space through the gas inlet.

Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

Abstract: Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

Abstract: Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer.

Abstract: A method of manufacturing a semiconductor device includes an improved technique of filling a trench to provide the resulting semiconductor device with better characteristics and higher reliability. The method includes forming a trench in a semiconductor layer, forming a first layer on the semiconductor layer using a silicon source and a nitrogen source to fill the trench, curing the first layer using an oxygen source, and annealing the second layer. The method may also be used to form other types of insulating layers such as an interlayer insulating layer.

Abstract: In some embodiments, a semiconductor substrate includes trenches defining active regions. The semiconductor device further includes lower and upper device isolation patterns disposed in the trenches. An intergate insulation pattern and a control gate electrode are disposed on the semiconductor substrate to cross over the active regions. A charge storage electrode is between the control gate electrode and the active regions. A gate insulation pattern is between the charge storage electrode and the active regions, and the intergate insulation pattern directly contacts the upper device isolation pattern between the active regions.

Abstract: A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer.

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

Abstract: A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

Abstract: A semiconductor device includes a substrate having a trench, a liner layer pattern on sidewalls and a bottom surface of the trench, the liner layer pattern including a first oxide layer pattern and a second oxide layer pattern, a diffusion blocking layer pattern on the liner layer pattern, and an isolation layer pattern in the trench on the diffusion blocking layer pattern.

Abstract: A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract: Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.