Patents by Inventor Yong-Sung Cho
Yong-Sung Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092228Abstract: A seat for a vehicle, includes a second row center seat and a second row side seat provided on a partition wall positioned rearward of a driver seat, the second row center seat may move leftward or rightward, and an interval between the seats may be increased in a state in which the second row center seat is moved in a right direction away from the second row side seat, which makes it possible to maximally prevent body contact between a passenger in the second row center seat and a passenger in the second row side seat.Type: ApplicationFiled: January 20, 2023Publication date: March 21, 2024Applicants: Hyundai Motor Company, Kia Corporation, Hyundai Transys Inc.Inventors: Jung Sang YOU, Yong Chul Kim, Dae Hee Lee, Eun Sue Kim, Jae Hoon Cho, Han Kyung Park, Jae Sung Shin, Hae Dong Kwak, Jun Sik Hwang, Gwon Hwa Bok
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Publication number: 20240067056Abstract: The present disclosure relates to a vehicle rear seat including: a center seat; and side seats located on the left and right of the center seat, wherein, the center seat is capable of protruding by moving the center seat forward with respect to the side seats, and in the state in which the center seat protrudes forward, it is possible to increase an inter-passenger distance so that physical contact between the passenger of the center seat and the passenger of each of the side seats can be prevented as much as possible.Type: ApplicationFiled: March 6, 2023Publication date: February 29, 2024Inventors: Jung Sang You, Yong Chul Kim, Dae Hee Lee, Eun Sue Kim, Jae Hoon Cho, Han Kyung Park, Jae Sung Shin, Hae Dong Kwak, Jun Sik Hwang, Gwon Hwa Bok
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Patent number: 11798641Abstract: A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.Type: GrantFiled: October 6, 2021Date of Patent: October 24, 2023Inventor: Yong-Sung Cho
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Patent number: 11574691Abstract: A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.Type: GrantFiled: September 1, 2020Date of Patent: February 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Yong-Sung Cho
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Patent number: 11508419Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.Type: GrantFiled: April 12, 2021Date of Patent: November 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Sung Cho, Jeung Hwan Park, Jong Min Kim, Jung Kwan Kim
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Publication number: 20220028468Abstract: A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Inventor: YONG-SUNG CHO
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Publication number: 20210233574Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Yong Sung CHO, Jeung Hwan PARK, Jong Min KIM, Jung Kwan KIM
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Patent number: 11004484Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.Type: GrantFiled: July 21, 2020Date of Patent: May 11, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Sung Cho, Jeung Hwan Park, Jong Min Kim, Jung Kwan Kim
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Patent number: 10902905Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line, and a second bias circuit inputting a second bias voltage to a selected bit line, a first switch element connected to the selected word line, and a second switch element connected between the first switch element and the first bias circuit; and a control logic configured to control the first and second switch elements, when a predetermined delay time elapses after the second bias voltage is input to the selected bit line. The control logic turns off the first switch element while the second switch element is turned on.Type: GrantFiled: September 22, 2019Date of Patent: January 26, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Sung Cho, Venkataramana Gangasani, Hee Won Kim, Tae Hui Na
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Publication number: 20200395088Abstract: A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.Type: ApplicationFiled: September 1, 2020Publication date: December 17, 2020Inventor: YONG-SUNG CHO
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Patent number: 10867672Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.Type: GrantFiled: July 3, 2019Date of Patent: December 15, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sung Cho, Moo-Sung Kim, Seung-You Baek, Jong-Min Baek, Bong-Kil Jung
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Publication number: 20200349985Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Inventors: Yong Sung CHO, Jeung Hwan PARK, Jong Min KIM, Jung Kwan KIM
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Publication number: 20200321046Abstract: A memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line, and a second bias circuit inputting a second bias voltage to a selected bit line, a first switch element connected to the selected word line, and a second switch element connected between the first switch element and the first bias circuit; and a control logic configured to control the first and second switch elements, when a predetermined delay time elapses after the second bias voltage is input to the selected bit line. The control logic turns off the first switch element while the second switch element is turned on.Type: ApplicationFiled: September 22, 2019Publication date: October 8, 2020Inventors: Yong Sung CHO, Venkataramana GANGASANI, Hee Won KIM, Tae Hui NA
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Patent number: 10789021Abstract: A memory device includes a memory cell array including a plurality of memory cells on which a programming loop is executed a plurality of times; a voltage generator configured to apply a verifying voltage to the memory cells, for verifying at least one programming state of the memory cells; and a voltage controller configured to control the voltage generator to change a level of the verifying voltage as a program loop count increases, based on temperature information about a temperature inside or outside the memory device.Type: GrantFiled: December 14, 2016Date of Patent: September 29, 2020Assignee: Volentine, Whitt & Francos, PLLCInventor: Yong-Sung Cho
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Patent number: 10720207Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.Type: GrantFiled: December 5, 2018Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Sung Cho, Jeung Hwan Park, Jong Min Kim, Jung Kwan Kim
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Publication number: 20200211646Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.Type: ApplicationFiled: July 3, 2019Publication date: July 2, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Yong-Sung CHO, Moo-Sung KIM, Seung-You BAEK, Jong-Min BAEK, Bong-Kil JUNG
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Patent number: 10600488Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.Type: GrantFiled: November 12, 2018Date of Patent: March 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-ho Song, Se-heon Baek, Yong-sung Cho
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Publication number: 20190385674Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.Type: ApplicationFiled: December 5, 2018Publication date: December 19, 2019Inventors: Yong Sung CHO, Jeung Hwan PARK, Jong Min KIM, Jung Kwan KIM
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Patent number: 10366769Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.Type: GrantFiled: November 13, 2017Date of Patent: July 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-sung Cho, Il-han Park, Jung-yun Yun, Youn-ho Hong
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Publication number: 20190080770Abstract: A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.Type: ApplicationFiled: November 12, 2018Publication date: March 14, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-ho SONG, Se-heon BAEK, Yong-sung CHO