Patents by Inventor Yong Tian Hou
Yong Tian Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210265479Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Yong-Tian HOU, Yuan-Shun CHAO, Chien-Hao CHEN, Cheng-Lung HUNG
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Patent number: 11004950Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.Type: GrantFiled: December 13, 2018Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
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Publication number: 20190131419Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.Type: ApplicationFiled: December 13, 2018Publication date: May 2, 2019Inventors: Yong-Tian HOU, Yuan-Shun CHAO, Chien-Hao CHEN, Cheng-Lung HUNG
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Patent number: 10164045Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.Type: GrantFiled: December 11, 2013Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
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Publication number: 20170207315Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.Type: ApplicationFiled: December 11, 2013Publication date: July 20, 2017Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
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Patent number: 9397184Abstract: A semiconductor device having metal gate includes a substrate, a metal gate positioned on the substrate, a high-k gate dielectric layer, and an epitaxial channel layer positioned in between the high-k gate dielectric layer and the substrate. A length of the epitaxial channel layer is larger than a length of the metal gate, and a bottom of the epitaxial channel layer and the substrate are coplanar.Type: GrantFiled: August 28, 2015Date of Patent: July 19, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventor: Yong Tian Hou
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Publication number: 20150372105Abstract: A semiconductor device having metal gate includes a substrate, a metal gate positioned on the substrate, a high-k gate dielectric layer, and an epitaxial channel layer positioned in between the high-k gate dielectric layer and the substrate. A length of the epitaxial channel layer is larger than a length of the metal gate, and a bottom of the epitaxial channel layer and the substrate are coplanar.Type: ApplicationFiled: August 28, 2015Publication date: December 24, 2015Inventor: Yong Tian Hou
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Publication number: 20150372114Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device formed thereon, and the first semiconductor device includes a first dummy gate. Next, the dummy gate is removed to form a first gate trench in the first semiconductor device, and the substrate is exposed in a bottom of the first gate trench. Subsequently, an epitaxial channel layer is formed in the first gate trench.Type: ApplicationFiled: August 27, 2015Publication date: December 24, 2015Inventor: Yong Tian Hou
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Publication number: 20150021681Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device formed thereon, and the first semiconductor device includes a first dummy gate. Next, the dummy gate is removed to form a first gate trench in the first semiconductor device, and the substrate is exposed in a bottom of the first gate trench. Subsequently, an epitaxial channel layer is formed in the first gate trench.Type: ApplicationFiled: July 16, 2013Publication date: January 22, 2015Inventor: Yong Tian Hou
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Patent number: 8836038Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.Type: GrantFiled: September 16, 2010Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, Kuo-Tai Huang, Tze-Liang Lee
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Publication number: 20140091402Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.Type: ApplicationFiled: December 11, 2013Publication date: April 3, 2014Inventors: Yong-Tian Hou, Donald Y. Chao, Chien-Hao Chen, Cheng-Lung Hung
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Patent number: 8679962Abstract: A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.Type: GrantFiled: November 4, 2008Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Chien-Hao Chen, Donald Y. Chao, Cheng-Lung Hung
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Patent number: 8536660Abstract: A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.Type: GrantFiled: March 12, 2008Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Fu Hsu, Yong-Tian Hou, Ssu-Yi Li, Kuo-Tai Huang, Mong Song Liang
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Patent number: 8384159Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.Type: GrantFiled: April 20, 2009Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Patent number: 8324090Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.Type: GrantFiled: December 18, 2008Date of Patent: December 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuri Masuoka, Peng-Fu Hsu, Huan-Tsung Huang, Kuo-Tai Huang, Yong-Tian Hou, Carlos H. Diaz
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Patent number: 8258546Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.Type: GrantFiled: July 20, 2011Date of Patent: September 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
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Publication number: 20110272766Abstract: A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
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Patent number: 7994051Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.Type: GrantFiled: October 17, 2008Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Hung, Yong-Tian Hou, Keh-Chiang Ku, Chien-Hao Huang
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Patent number: 7989321Abstract: A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.Type: GrantFiled: October 23, 2008Date of Patent: August 2, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Yong-Tian Hou, Peng-Fu Hsu, Kuo-Tai Huang, Donald Y. Chao, Cheng-Lung Hung
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Patent number: 7871915Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).Type: GrantFiled: March 26, 2009Date of Patent: January 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Soon Lim, Yong-Tian Hou, Chien-Hao Chen, Chi-Chun Chen