Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

Abstract: A transmitter includes a driver circuit configured to drive a channel connected to a first node by controlling a turn-on impedance of a pull-up path, a turn on impedance of a pull-down path, or both according to a plurality of control signals; an encoder configured to generate the plurality of control signals according to a multi-bit data and a calibration signal; and a calibration circuit configured to generate the calibration signal including calibration information corresponding to the plurality of control signals, wherein the encoder determines activation and magnitude of each of the plurality of control signals according to the multi-bit data and the calibration information.

Abstract: A transmitter includes a driver circuit configured to drive a channel connected to a first node by controlling a turn-on impedance of a pull-up path, a turn on impedance of a pull-down path, or both according to a plurality of control signals; an encoder configured to generate the plurality of control signals according to a multi-bit data and a calibration signal; and a calibration circuit configured to generate the calibration signal including calibration information corresponding to the plurality of control signals, wherein the encoder determines activation and magnitude of each of the plurality of control signals according to the multi-bit data and the calibration information.