Abstract: A method for making a metallogenic series map of mineral deposits is disclosed. The method includes making a list of mineral varieties and mineral producing areas, determining typical mineral deposits, making a geotectonic map, determining a mineral deposit model by combining the typical mineral deposits and metallogenic geotectonic background conditions, compiling a synthem-stratum-magma-mineralization histogram, obtaining regional metallogenetic regularities, selecting a geographic layer as a base map, and making the metallogenic series map of mineral deposits on the basis of the base map according to the regional metallogenetic regularities. The metallogenic series map of mineral deposits of the present disclosure is a regional metallogenetic map which not only reflects the mineral variety, scale, type and epoch of mineral deposits in different geotectonic environments but also reflects the relationship between mineral deposits and mineral deposit combinations to form a “five-in-one” legend.

Abstract: The invention discloses a data structure-aware prefetching method and device on a graphics processing unit. The method comprises the steps of acquiring information for a memory access request in which a monitoring processor checks a graph data structure and read data, using a data structure access mode defined by a breadth first search and graph data structure information to generate four corresponding vector prefetching requests and store into a prefetching request queue. The device comprises a data prefetching unit distributed into each processing unit, each data prefetching unit is respectively connected with an memory access monitor, a response FIFO and a primary cache of a load/store unit, and comprises an address space classifier, a runtime information table, prefetching request generation units and the prefetching request queue.

Abstract: The invention discloses a data structure-aware prefetching method and device on a graphics processing unit. The method comprises the steps of acquiring information for a memory access request in which a monitoring processor checks a graph data structure and read data, using a data structure access mode defined by a breadth first search and graph data structure information to generate four corresponding vector prefetching requests and store into a prefetching request queue. The device comprises a data prefetching unit distributed into each processing unit, each data prefetching unit is respectively connected with an memory access monitor, a response FIFO and a primary cache of a load/store unit, and comprises an address space classifier, a runtime information table, prefetching request generation units and the prefetching request queue.

Abstract: A close-coupling shared storage architecture of double-wing expandable multiprocessor is provided in the close-coupling shared storage architecture with p processors scale, the close-coupling shared storage architecture of double-wing expandable multiprocessor comprises: j processor modules PMs; wherein, each processor module is formed by coupling and cross-jointing i processors Cs, and each processor is directly connected with a node controller NC through only one link; each processor module PM comprises 2 pairing node controllers NCs, and each node controller NC is connected with the processors through m links and is connected with an interconnect network through n links; the interconnect network comprises two groups, and each group comprises k cross switch route chips NRs, each of which has q ports. By adopting the connection method above, the close-coupling shared storage architecture of double-wing expandable multiprocessor is formed.

Abstract: A close-coupling shared storage architecture of double-wing expandable multiprocessor is provided in the close-coupling shared storage architecture with p processors scale, the close-coupling shared storage architecture of double-wing expandable multiprocessor comprises: j processor modules PMs; wherein, each processor module is formed by coupling and cross-jointing i processors Cs, and each processor is directly connected with a node controller NC through only one link; each processor module PM comprises 2 pairing node controllers NCs, and each node controller NC is connected with the processors through m links and is connected with an interconnect network through n links; the interconnect network comprises two groups, and each group comprises k cross switch route chips NRs, each of which has q ports. By adopting the connection method above, the close-coupling shared storage architecture of double-wing expandable multiprocessor is formed.