Abstract: A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.

Abstract: A clock and data recovery circuit includes a phase interpolation circuit that adjusts a phase of a reference clock signal generated by a reference clock generation circuit to generate a reception clock signal, a filter that performs filter processing on a data signal output from an ADC that converts an analog data signal to a digital data signal in synchronization with the clock signal, a phase comparison circuit that outputs phase difference data between a transmission-side clock signal and the reference clock signal based on an output of the filter, and a loop filter that generates phase data to be set in the phase interpolation circuit. The filter includes an FIR filter with a tap number N, and an FIR filter with a tap number N+1 that outputs a signal delayed by half a clock than the former FIR filter.

Abstract: A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.

Abstract: A clock and data recovery circuit includes a phase interpolation circuit that adjusts a phase of a reference clock signal generated by a reference clock generation circuit to generate a reception clock signal, a filter that performs filter processing on a data signal output from an ADC that converts an analog data signal to a digital data signal in synchronization with the clock signal, a phase comparison circuit that outputs phase difference data between a transmission-side clock signal and the reference clock signal based on an output of the filter, and a loop filter that generates phase data to be set in the phase interpolation circuit. The filter includes an FIR filter with a tap number N, and an FIR filter with a tap number N+1 that outputs a signal delayed by half a clock than the former FIR filter.