Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

Abstract: An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components.

Abstract: A wireless IC interconnect system and method facilitates interconnections between first and second IC locations via a wireless transmission medium; the IC locations may be on the same chip or on separate chips. A signal to be conveyed is modulated, and the modulated signal is capacitively coupled to the wireless transmission medium—preferably a properly terminated microstrip transmission line (MTL) or a coplanar waveguide (CPW). The modulated signal is capacitively coupled from the wireless medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. In a preferred embodiment, the wireless transmission system conveys numerous signals simultaneously, with the signals modulated and demodulated with multiple access algorithms such as code-division (CDMA) and/or frequency-division (FDMA) multiple access algorithms.

Abstract: A low-profile cavity-backed slot antenna is disclosed including a cavity substrate having a slot with a resonant frequency and a uniplanar compact photonic band-gap (UC-PBG) substrate, proximate to the cavity substrate and having a two-dimensional periodic metallic pattern on a dielectric slab and a ground plane, wherein the UC-PBG substrate behaves substantially as an open boundary at the resonant frequency of the slot. The slot antenna has reduced height while maintaining good performance.

Abstract: A wireless IC interconnect system and method facilitates interconnections between first and second IC locations via a wireless transmission medium; the IC locations may be on the same chip or on separate chips. A signal to be conveyed is modulated, and the modulated signal is capacitively coupled to the wireless transmission medium—preferably a properly terminated microstrip transmission line (MTL) or a coplanar waveguide (CPW). The modulated signal is capacitively coupled from the wireless medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. In a preferred embodiment, the wireless transmission system conveys numerous signals simultaneously, with the signals modulated and demodulated with multiple access algorithms such as code-division (CDMA) and/or frequency-division (FDMA) multiple access algorithms.

Abstract: A low-profile cavity-backed slot antenna is disclosed including a cavity substrate having a slot with a resonant frequency and a unilanar compact photonic band-gap (UC-PBG) substrate proximate to the cavity substrate and having a two-dimensional periodic metallic pattern on a dielectric slab and a ground plane, wherein the UC-PBG substrate behaves substantially as an open boundary at the resonant frequency of the slot. The slot antenna has reduced height while maintaining good performance.