Patents by Inventor Yongxi Zhang
Yongxi Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967123Abstract: Provided is a binarization method for CT sectional image of fiber package containing artifacts, which includes: performing brightness adjustment on the source image obtained after converting of the HSV image model by using a composite tangent function; creating a planar morphological structural element having a morphology similar to that of a target object to obtain a background image without the target object; obtaining a second intermediate image by a subtraction operation of the first intermediate image and the background image; improving an image contrast of the second intermediate image again to obtain a third intermediate image; and binarizing the third intermediate image by using a local adaptive threshold binarization algorithm and removing a background noise to obtain a final binarized image. The binarization method can improve the uneven brightness of the image under complex illumination, alleviate the artifacts, and strip similar objects from the background with similar gray scales.Type: GrantFiled: November 1, 2023Date of Patent: April 23, 2024Assignee: XIDIAN UNIVERSITYInventors: Tengyin Shi, Yiqun Zhang, Zhuo Zhang, Hongzhang Feng, Shen Li, Dongwu Yang, Naigang Hu, Yongxi He
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Publication number: 20230070151Abstract: A second-life battery-based super multi-objective energy management method for a smart community microgrid, including: establishing a residual life decay model of the second-life battery based on a residual charge and discharge cycle number; establishing a super multi-objective energy management model based on residential energy consumption costs, the residual life decay model of the second-life battery, residential electricity consumption behaviors, and impacts of residential community load on an electricity distribution system; recording state information of the second-life battery in the smart community; collecting residential electricity consumption information in the smart community, and predicting a renewable energy output value of the smart community; and solving the super multi-objective energy management model by using a NSGA-III algorithm combining with the state information of the second-life battery and the renewable energy output value.Type: ApplicationFiled: November 16, 2022Publication date: March 9, 2023Inventors: Yongxi ZHANG, Youjun DENG, Yuanyuan WANG, Gongping WU
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Patent number: 10937905Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.Type: GrantFiled: May 23, 2014Date of Patent: March 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Philip L. Hower, Sameer P. Pendharkar, John Lin, Guru Mathur, Scott Balster, Victor Sinow
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Patent number: 10601422Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: GrantFiled: November 10, 2017Date of Patent: March 24, 2020Assignee: Texas Instruments IncorporatedInventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Patent number: 10319809Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.Type: GrantFiled: December 15, 2017Date of Patent: June 11, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P. Pendharkar
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Patent number: 10304719Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.Type: GrantFiled: January 23, 2017Date of Patent: May 28, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Eugen Mindricelu, Sameer Pendharkar, Seetharaman Sridhar
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Patent number: 10121891Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.Type: GrantFiled: November 30, 2016Date of Patent: November 6, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar, Henry Litzmann Edwards
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Patent number: 9985028Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.Type: GrantFiled: April 19, 2017Date of Patent: May 29, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar, Scott G. Balster
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Publication number: 20180108729Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.Type: ApplicationFiled: December 15, 2017Publication date: April 19, 2018Inventors: Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P. Pendharkar
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Publication number: 20180097517Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: ApplicationFiled: November 10, 2017Publication date: April 5, 2018Inventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Patent number: 9876071Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.Type: GrantFiled: February 28, 2015Date of Patent: January 23, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Philip L Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P Pendharkar
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Patent number: 9843322Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: GrantFiled: March 11, 2016Date of Patent: December 12, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Patent number: 9806074Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.Type: GrantFiled: December 10, 2015Date of Patent: October 31, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar
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Publication number: 20170264289Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: ApplicationFiled: March 11, 2016Publication date: September 14, 2017Inventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Patent number: 9735265Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.Type: GrantFiled: November 10, 2016Date of Patent: August 15, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer Pendharkar, Seetharaman Sridhar
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Publication number: 20170221896Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Yongxi ZHANG, Sameer P. PENDHARKAR, Scott G. BALSTER
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Patent number: 9653577Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.Type: GrantFiled: July 27, 2016Date of Patent: May 16, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar, Scott G. Balster
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Publication number: 20170133261Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.Type: ApplicationFiled: January 23, 2017Publication date: May 11, 2017Inventors: Yongxi Zhang, Eugen Mindricelu, Sameer Pendharkar, Seetharaman Sridhar
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Publication number: 20170084738Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.Type: ApplicationFiled: November 30, 2016Publication date: March 23, 2017Inventors: Yongxi Zhang, Sameer P. Pendharkar, Henry Litzmann Edwards
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Publication number: 20170062611Abstract: An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.Type: ApplicationFiled: November 10, 2016Publication date: March 2, 2017Inventors: Yongxi ZHANG, Sameer PENDHARKAR, Seetharaman SRIDHAR