Abstract: A shift register unit, a method of driving the same, a gate driving circuit and a display device are provided. The shift register unit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit, a pull-down node switching control circuit, and a gate driving output circuit. The pull-down node switching control circuit is configured to control the first control voltage signal to be written into the first pull-down node and control the second control voltage signal to be written into the second pull-down node under the control of a frame reset control signal. The gate driving output circuit is configured to control a gate driving signal outputted by a gate driving signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node, and the voltage signal of the second pull-down node.

Abstract: A shift register unit including a first output circuit configured to transfer a clock signal at a clock signal terminal to a signal output terminal as an output signal in response to a first node being at an active potential, a second output circuit configured to transfer the clock signal at the clock signal terminal to a carry output terminal as a carry output signal in response to the first node being at the active potential, and a delay circuit configured to generate a delayed version of a carry input signal in response to the carry input signal at a carry input terminal being active, and to transfer an inactive voltage at a first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.

Abstract: A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

Abstract: This disclosure provides a method for treating an etching waste liquid from an etching process of indium tin oxide comprising hydrochloric acid, acetic acid, tin ions, indium ions and water, comprising the steps of: distilling the etching waste liquid to obtain a distillate comprising hydrochloric acid and acetic acid and a post-distillation liquid comprising tin ions and indium ions; generating a precipitate by reacting tin ions in the post-distillation liquid with sulfide ions to remove tin ions from the solution so as to obtain a post-precipitation solution containing indium ions; and electrolyzing the post-precipitation solution to obtain crude indium.

Abstract: This disclosure provides a method for treating an etching waste liquid from an etching process of indium tin oxide comprising hydrochloric acid, acetic acid, tin ions, indium ions and water, comprising the steps of: distilling the etching waste liquid to obtain a distillate comprising hydrochloric acid and acetic acid and a post-distillation liquid comprising tin ions and indium ions; generating a precipitate by reacting tin ions in the post-distillation liquid with sulfide ions to remove tin ions from the solution so as to obtain a post-precipitation solution containing indium ions; and electrolyzing the post-precipitation solution to obtain crude indium.

Abstract: A power supply, comprising a constant-current power supply, and at least two current-limiting protection branches (I1, . . . , In) connected in parallel on the output loop of the constant-current power supply, the current limiting protection branches comprising at least one load (L1, . . . , Lnn) and current-limiting protector (l0, . . . , ln), and the designed current limiting value of the current-limiting protector in each branch being greater than the designed working current value of the current-limiting protection branch where the current-limiting protector is located.