Patents by Inventor Yongxiang Wen

Yongxiang Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11305985
    Abstract: A MEMS device and a manufacturing method thereof. The manufacturing method comprises: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module. Forming the MEMS module comprises: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 19, 2022
    Assignees: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD., HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventors: Wei Sun, Yongxiang Wen, Chen Liu, Junshan Ge, Zhijian Ma
  • Patent number: 11212611
    Abstract: A MEMS microphone and a manufacturing method thereof. The method comprises: sequentially forming a first isolation layer, a diaphragm, and a second isolation layer on a substrate; sequentially forming a first protective layer, a backplate electrode, and a second protective layer on the second isolation layer; forming a release hole penetrating through the first protective layer, the backplate electrode, and the second protective layer; forming an acoustic cavity penetrating through the substrate; releasing the diaphragm through the acoustic cavity and the release hole; and forming a groove on a surface of the first isolation layer, wherein the diaphragm conformally covers the surface of the first isolation layer, thereby forming a spring structure at a position of the groove.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: December 28, 2021
    Assignees: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD., HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventors: Yongxiang Wen, Fuhe Sun, Chen Liu, Wenchao Jin, Wenliang Sun
  • Patent number: 11161734
    Abstract: Disclosed a MEMS assembly and a manufacturing method thereof. The manufacturing method comprises: forming a groove on a sensor chip; forming a bonding pad on a circuit chip; bonding the sensor chip and the circuit chip together to form a bonding assembly; performing a first dicing process at a first position of the sensor chip to penetrate through the sensor chip to the groove; performing a second dicing process at a second position of the sensor chip to penetrate through the sensor chip and the circuit chip, for obtaining an individual MEMS assembly by singulating the bonding assembly, wherein location of the groove corresponds to a position of the bonding pad, and an opening is formed in the sensor chip to expose the bonding pad when the second dicing process is performed. The method uses two dicing process respectively achieving different depths to expose the bonding pad of the sensor chip and singulate the MEMS assembly, respectively, to improve yield and reliability.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 2, 2021
    Assignees: HANGZHOU SILAN INTEGRATED CIRCUITS CO., LTD., HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventors: Yongxiang Wen, Chen Liu, Feng Ji, XiaoLi Zhang
  • Publication number: 20210168497
    Abstract: A MEMS microphone and a manufacturing method thereof. The method comprises: sequentially forming a first isolation layer, a diaphragm, and a second isolation layer on a substrate; sequentially forming a first protective layer, a backplate electrode, and a second protective layer on the second isolation layer; forming a release hole penetrating through the first protective layer, the backplate electrode, and the second protective layer; forming an acoustic cavity penetrating through the substrate; releasing the diaphragm through the acoustic cavity and the release hole; and forming a groove on a surface of the first isolation layer, wherein the diaphragm conformally covers the surface of the first isolation layer, thereby forming a spring structure at a position of the groove.
    Type: Application
    Filed: January 23, 2020
    Publication date: June 3, 2021
    Inventors: Yongxiang Wen, Fuhe Sun, Chen Liu, Wenchao Jin, Wenliang Sun
  • Publication number: 20200391996
    Abstract: A MEMS device and a manufacturing method thereof. The manufacturing method comprises: forming a CMOS circuit; and forming a MEMS module on the CMOS circuit which is coupling to the MEMS module and configured to drive the MEMS module. Forming the MEMS module comprises: forming a protective layer; forming a sacrificial layer in the protective layer; forming a first electrode on the protective layer and on the sacrificial layer so that the first electrode covers the sacrificial layer, and electrically coupling the first electrode to the CMOS circuit; forming a piezoelectric layer on the first electrode and above the sacrificial layer; forming a second electrode on the piezoelectric layer and electrically coupling the second electrode to the CMOS circuit; forming a through hole to reach the sacrificial layer; and forming a cavity by removing the sacrificial layer through the through hole.
    Type: Application
    Filed: March 25, 2019
    Publication date: December 17, 2020
    Inventors: Wei Sun, Yongxiang Wen, Chen Liu, Junshan GE, Zhijian Ma
  • Patent number: 10770340
    Abstract: The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: September 8, 2020
    Assignees: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD., HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventors: Yongxiang Wen, Shaohua Zhang, Yulei Jiang, Yanghui Sun, Guoqiang Yu
  • Publication number: 20200255286
    Abstract: Disclosed a MEMS assembly and a manufacturing method thereof. The manufacturing method comprises: forming a groove on a sensor chip; forming a bonding pad on a circuit chip; bonding the sensor chip and the circuit chip together to form a bonding assembly; performing a first dicing process at a first position of the sensor chip to penetrate through the sensor chip to the groove; performing a second dicing process at a second position of the sensor chip to penetrate through the sensor chip and the circuit chip, for obtaining an individual MEMS assembly by singulating the bonding assembly, wherein location of the groove corresponds to a position of the bonding pad, and an opening is formed in the sensor chip to expose the bonding pad when the second dicing process is performed. The method uses two dicing process respectively achieving different depths to expose the bonding pad of the sensor chip and singulate the MEMS assembly, respectively, to improve yield and reliability.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 13, 2020
    Inventors: Yongxiang Wen, Chen Liu, Feng Ji, XiaoLi Zhang
  • Patent number: 10513431
    Abstract: A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 24, 2019
    Assignee: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD
    Inventors: Yongxiang Wen, Chen Liu, Feng Ji, Liwen Li
  • Publication number: 20180362339
    Abstract: A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed.
    Type: Application
    Filed: August 22, 2018
    Publication date: December 20, 2018
    Applicant: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD
    Inventors: Yongxiang WEN, Chen LIU, Feng JI, Liwen LI
  • Patent number: 10081541
    Abstract: A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 25, 2018
    Assignee: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD
    Inventors: Yongxiang Wen, Chen Liu, Feng Ji, Liwen Li
  • Publication number: 20180033676
    Abstract: The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Applicants: HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD., HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventors: Yongxiang WEN, Shaohua ZHANG, Yulei JIANG, Yanghui SUN, Guoqiang YU
  • Patent number: 9824913
    Abstract: The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: November 21, 2017
    Assignees: Hangzhou Silan Integrated Circuit Co., Ltd., Hangzhou Silan Microelectronics Co., Ltd.
    Inventors: Yongxiang Wen, Shaohua Zhang, Yulei Jiang, Yanghui Sun, Guoqiang Yu
  • Publication number: 20170081176
    Abstract: The invention provides a MEMS device, semiconductor device, and method for manufacturing the same. The MEMS device comprises an enclosed cavity, the cavity having an inner wall extending in a first plane, the inner wall including a film deposition region for depositing a getter film, wherein one or more grooves are formed in the film deposition region, the angle between the sidewalls of the grooves and the first plane is more than 0° and less than 180°, and the getter film overlays the sidewall of the grooves. The invention can form the getter film in a smaller incident flux angle with a common sputtering, evaporation apparatus, that is, form the porous, high roughness getter.
    Type: Application
    Filed: December 28, 2015
    Publication date: March 23, 2017
    Applicants: HANGZHOU SILAN MICROELECTRONICS CO., LTD., HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD
    Inventors: Feng JI, Yongxiang WEN, Chen LIU, Hao ZHOU
  • Publication number: 20150179497
    Abstract: The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage BCD process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the BCD high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the BCD process.
    Type: Application
    Filed: March 29, 2013
    Publication date: June 25, 2015
    Applicants: HANGZHOU SILAN MICROELECTRONICS CO., LTD., HANGZHOU SILAN INTEGRATED CIRCUIT CO., LTD
    Inventors: Yongxiang Wen, Shaohua Zhang, Yulei Jiang, Yanghui Sun, Guoqiang Yu
  • Publication number: 20150091140
    Abstract: A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S11, providing a MEMS sealing cap silicon substrate (100); step S12, forming n stacked mask layers (101, 102, 103) on the MEMS sealing cap silicon substrate (100), after forming each mask layer, photolithographing and etching the mask layer and all other mask layers beneath the same to form a plurality of etching windows (D1, D2, D3); step S13, etching the MEMS sealing cap silicon substrate by using the current uppermost mask layer and a layer of mask material beneath the same as a mask; step S14, removing the current uppermost mask layer; step S15, repeating the step S13 and the step S14 until all the n mask layers are removed.
    Type: Application
    Filed: March 18, 2013
    Publication date: April 2, 2015
    Inventors: Yongxiang Wen, Chen Liu, Feng Ji, Liwen Li