Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes sub-pixels, at least part of the sub-pixels include a light emitting element, the light emitting element includes a light emitting functional layer, and a first electrode and a second electrode, the first electrode is located between the light emitting functional layer and the base substrate, and the light emitting functional layer includes film layers; the display substrate further includes a first defining structure located between at least two adjacent sub-pixels, the first defining structure includes an end portion located between the light emitting functional layer and the first electrode, and the first electrode overlaps with the end portion in the direction perpendicular to the base substrate; at least one of the film layers in at least one sub-pixel is disconnected at the end portion of the first defining structure.

Abstract: Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a display region and at least one hole region located in the display region, the hole region includes a function hole and a partition region surrounding the function hole, the partition region is provided with at least one partition dam surrounding the function hole; the partition dam includes a first partition layer disposed on a base substrate and a second partition layer disposed on a side of the first partition layer away from the base substrate, at least one partition layer includes a second sub-layer and a third sub-layer disposed on a side of the second sub-layer away from the base substrate, the third sub-layer has a protrusion with respect to a sidewall of the second sub-layer, and the protrusion and the sidewall of the second sub-layer form an inwardly recessed structure.

Abstract: The present disclosure relates to an ion implantation amount adjustment device that includes: an adjuster configured to turn on or off an ion outlet of the ion implantation apparatus; and an actuator configured to control movement of the adjuster to adjust an opening degree of the ion outlet.

Abstract: A bearing device and an ion implantation device are provided. The bearing device includes a bearing table configured to bear a substrate, and a plurality of supporting components configured to support the substrate, each supporting component is movably arranged on the bearing table, to support the substrate at an adjustable position.

Abstract: The present disclosure relates to an ion implantation amount adjustment device that includes: an adjuster configured to turn on or off an ion outlet of the ion implantation apparatus; and an actuator configured to control movement of the adjuster to adjust an opening degree of the ion outlet.

Abstract: A bearing device and an ion implantation device are provided. The bearing device includes a bearing table configured to bear a substrate, and a plurality of supporting components configured to support the substrate, each supporting component is movably arranged on the bearing table, to support the substrate at an adjustable position.

Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.

Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.