Patents by Inventor Yongyi FU

Yongyi FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240306428
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes sub-pixels, at least part of the sub-pixels include a light emitting element, the light emitting element includes a light emitting functional layer, and a first electrode and a second electrode, the first electrode is located between the light emitting functional layer and the base substrate, and the light emitting functional layer includes film layers; the display substrate further includes a first defining structure located between at least two adjacent sub-pixels, the first defining structure includes an end portion located between the light emitting functional layer and the first electrode, and the first electrode overlaps with the end portion in the direction perpendicular to the base substrate; at least one of the film layers in at least one sub-pixel is disconnected at the end portion of the first defining structure.
    Type: Application
    Filed: April 24, 2022
    Publication date: September 12, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Sa Liu, Yongyi Fu, Hexiong Li, Yong Zhou, Feng Bai
  • Publication number: 20240224716
    Abstract: Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a display region and at least one hole region located in the display region, the hole region includes a function hole and a partition region surrounding the function hole, the partition region is provided with at least one partition dam surrounding the function hole; the partition dam includes a first partition layer disposed on a base substrate and a second partition layer disposed on a side of the first partition layer away from the base substrate, at least one partition layer includes a second sub-layer and a third sub-layer disposed on a side of the second sub-layer away from the base substrate, the third sub-layer has a protrusion with respect to a sidewall of the second sub-layer, and the protrusion and the sidewall of the second sub-layer form an inwardly recessed structure.
    Type: Application
    Filed: November 29, 2021
    Publication date: July 4, 2024
    Inventors: Nan DU, Guowei SU, ChiehHsing CHUNG, Yongyi FU, Yong ZHOU, Feng BAI, Saijun SUN, Kaihao CHEN, Suoping PENG, Kechao SONG, Zhengping XU, Sa LIU, Hexiong LI
  • Patent number: 10734189
    Abstract: The present disclosure relates to an ion implantation amount adjustment device that includes: an adjuster configured to turn on or off an ion outlet of the ion implantation apparatus; and an actuator configured to control movement of the adjuster to adjust an opening degree of the ion outlet.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 4, 2020
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hao Jing, Dongwoo Kang, Yongyi Fu, Chenliang Liu, Rujian Li, Kang Luo
  • Patent number: 10598220
    Abstract: A bearing device and an ion implantation device are provided. The bearing device includes a bearing table configured to bear a substrate, and a plurality of supporting components configured to support the substrate, each supporting component is movably arranged on the bearing table, to support the substrate at an adjustable position.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 24, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chenliang Liu, Donghua Jiang, Yongyi Fu, Chao Tan, Xuewei Wang, Rujian Li, Kang Luo, Yongzhou Ling, Yin Xie, Jianbo Yang, Fei Li
  • Publication number: 20190164718
    Abstract: The present disclosure relates to an ion implantation amount adjustment device that includes: an adjuster configured to turn on or off an ion outlet of the ion implantation apparatus; and an actuator configured to control movement of the adjuster to adjust an opening degree of the ion outlet.
    Type: Application
    Filed: March 28, 2018
    Publication date: May 30, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hao JING, Dongwoo KANG, Yongyi FU, Chenliang LIU, Rujian LI, Kang LUO
  • Publication number: 20180258988
    Abstract: A bearing device and an ion implantation device are provided. The bearing device includes a bearing table configured to bear a substrate, and a plurality of supporting components configured to support the substrate, each supporting component is movably arranged on the bearing table, to support the substrate at an adjustable position.
    Type: Application
    Filed: November 17, 2017
    Publication date: September 13, 2018
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chenliang LIU, Donghua JIANG, Yongyi FU, Chao TAN, Xuewei WANG, Rujian LI, Kang LUO, Yongzhou LING, Yin XIE, Jianbo YANG, Fei LI
  • Patent number: 9564354
    Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: February 7, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Byung Chun Lee, Donghua Jiang, Yongyi Fu, Wuyang Zhao, Chundong Li
  • Publication number: 20150303099
    Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.
    Type: Application
    Filed: December 3, 2013
    Publication date: October 22, 2015
    Inventors: Byung Chun LEE, Donghua JIANG, Yongyi FU, Wuyang ZHAO, Chundong LI