Patents by Inventor Yongyu Wu

Yongyu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056011
    Abstract: A method for lossless ARGB (Alpha, Red, Green, Blue) compression based on an intra-block prediction is provided. The method is executed by a processor, and the method comprises for an input image block under a processing channel, executing the following operations until all input image blocks are encoded: obtaining a predicted value of the input image block under a current processing channel based on the input image block under the current processing channel by the intra-block prediction; determining predicted residuals of the input image block under the current processing channel based on the predicted value and an original pixel value; inputting the predicted residuals into a residual encoder for encoding to obtain a residual stream of the input image block under the current processing channel; and storing residual streams of all input image blocks of all processing channels as a compressed file in a storage file.
    Type: Application
    Filed: October 25, 2024
    Publication date: February 13, 2025
    Applicants: ZHEJIANG UNIVERSITY, BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kai XU, Bo WU, Chenggang XU, Yanning CHEN, Fang LIU, Dawei GAO, Yongyu WU
  • Publication number: 20250056829
    Abstract: Provided are a DEMOS device and a method for producing the same. The DEMOS device includes a silicon substrate, a well region, a source region, a drain region, a drift region, a lightly doped region, a gate structure, and a field plate structure. The gate structure includes a primary gate structure and a secondary gate structure. The primary gate structure is disposed on a p-type well or an n-type well of the well region, and configured to receive an input signal. The secondary gate structure covers part of the p-type well and part of the drift region, or part of the n-type well and part of the drift region. The secondary gate structure is configured to receive a fixed bias voltage. The short gate length of the primary gate structure significantly reduces gate-drain capacitance, and increases cutoff frequency, enhancing high-frequency performance, while having minimal impact on breakdown voltage.
    Type: Application
    Filed: October 24, 2024
    Publication date: February 13, 2025
    Applicants: ZHEJIANG UNIVERSITY, BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kai XU, Bo WU, Xiaoyun HUANG, Yanning CHEN, Fang LIU, Dawei GAO, Yongyu WU
  • Patent number: D960130
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 9, 2022
    Assignee: BEIJING EDIFIER TECHNOLOGY CO., LTD
    Inventors: Bo Rong, Yongyu Wu
  • Patent number: D1056488
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: January 7, 2025
    Assignee: BEIJING EDIFIER TECHNOLOGY CO., LTD
    Inventors: Bo Rong, Sonia Xinyang Zhang, Yongyu Wu