Abstract: A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.

Abstract: This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by etching a bottom surface of the top portion of the trench then silicon etching to open a bottom portion of the trench with a slightly smaller width than the top portion of the trench. The method further includes a step of growing a thick oxide layer along sidewalls of the bottom portion of the trench thus forming a bird-beak shaped layer at an interface point between the top portion and bottom portion of the trench.

Abstract: This invention discloses a trenched semiconductor power device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with a bottom insulation layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of the bottom insulation attached to sidewalls of the trench extending above a top surface of the bottom trench-filling segment.

Abstract: A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.

Abstract: This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.

Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

Abstract: A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.

Abstract: This invention discloses a one-time programmable (OTP) memory cell. The OTP memory cell includes a dielectric layer disposed between two conductive polysilicon segments wherein the dielectric layer is ready to change from a non-conductive state to a conductive state through an induced voltage breakdown. In a preferred embodiment, one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer. In a preferred embodiment, the dielectric layer is further formed as sidewalls covering the edges and corners of a first polysilicon segments to conveniently induce a voltage breakdown in the dielectric layer by the edge and corner electrical field effects.

Abstract: A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.

Abstract: A method of performing a programming, testing and trimming operation is disclosed in this invention. The method includes a step of applying a programming circuit for programming an OTP memory for probing and sensing one of three different states of the OTP memory for carrying out a trimming operation using one of the three states of the OTP memory whereby a higher utilization of OTP memory cells is achieved. Selecting and programming two conductive circuits of the OTP into two different operational characteristics thus enables the storing and sensing one of the three different states of the OTP memory. These two conductive circuits may include two different transistors for programming into a linear resistor and a nonlinear resistor with different current conducting characteristics. The programming processes include application of a high voltage and different programming currents thus generating different operational characteristics of these two transistors.

Abstract: This invention discloses a one-time programmable (OTP) memory cell. The OTP memory cell includes a dielectric layer disposed between two conductive polysilicon segments wherein the dielectric layer is ready to change from a non-conductive state to a conductive state through an induced voltage breakdown. In a preferred embodiment, one of the conductive polysilicon segments further includes an etch undercut configuration for conveniently inducing the voltage breakdown in the dielectric layer. In a preferred embodiment, the dielectric layer is further formed as sidewalls covering the edges and corners of a first polysilicon segments to conveniently induce a voltage breakdown in the dielectric layer by the edge and corner electrical field effects.

Abstract: One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for each word line, at least one diode structure formed on the substrate and having first and second diodes, each diode having a cathode and an anode, wherein the word line is connected to the cathode of the first diode and to the anode of the second diode.

Abstract: A process of fabricating a semiconductor device includes forming a device region including a non-volatile memory element and forming a utility layer overlying the device region, where the utility layer is a dielectric material formed by RTCVD. The utility layer preferably has a hydrogen content below that necessary to reduce the data retention of the non-volatile memory element in the device region. The utility layer can function as one or more of an etch-stop layer, a diffusion barrier layer, or an insulating layer.

Abstract: An EEPROM memory device includes a substrate of a first conductivity type having a cell well region of a second conductivity type therein. A floating-gate transistor of the first conductivity type resides in the cell well region and includes a first region separated from a second region by a channel region. A write transistor of the second conductivity type resides in the substrate and includes a first region separated from a second region by a channel region. The second region partially extends into the cell well region and forms a p-n junction with the second region of the floating-gate transistor. The process for fabricating the EEPROM device includes forming the cell well region in the substrate by creating a retrograde doping profile. In operation, the EEPROM device transfers electrons between the cell well region and the floating-gate electrode during both programming and erasing operations.

Abstract: High voltage (HV), single polysilicon gate NMOS and PMOS transistors in double polysilicon stacked gate flash technology and methods for making the same are described. Specifically, the methods provide for the formation of (and devices comprise) high voltage polysilicon 1 and polysilicon 2 transistors (NMOS and PMOS) in double polysilicon stacked gate flash technology. Different types of transistors (e.g., HV P1 NMOS, HV P1 PMOS, HV P2 NMOS, HV P2 PMOS, LV P1 NMOS, LV P1 PMOS, LV P2 NMOS, LV P2 PMOS) are formed along with a stacked-gate double-poly transistor, thereby providing versatility in flash technology device design. The polysilicon 1 transistors may be salicided without adding to the complexity of the double poly stacked gate fabrication process. In addition, the stacked gate device may include polysilicon 2 only transistors.

Abstract: An EEPROM device incorporates a partially encapsulated floating gate electrode in order to increase the capacitive coupling between the floating gate electrode and the control gate region of an EEPROM device. The floating gate electrode is partially encapsulated by a capacitor plate that is locally interconnected to the control gate region residing in a semiconductor substrate. The capacitor plate is electrically isolated from the floating gate electrode by a capacitor dielectric layer overlying the floating gate electrode. By partially encapsulating the floating gate electrode with a capacitor plate electrically connected to the control gate region, a high capacitance coupling is obtained between the floating gate electrode and the control gate region, while minimizing the substrate area necessary for fabrication of the capacitor portion of an EEPROM device.

Abstract: An EEPROM cell includes a sense transistor and a select transistor, each having a first active region (110, 114) formed in a substrate, and sharing a second active region (112). The EEPROM cell may also include a floating gate (125) having a first portion (FG2) forming a gate region for said sense transistor, and a second portion (FG1) overlying the second active region and forming a program junction with said second active region. The first portion of said floating gate has a concentration of an impurity greater than a concentration of said impurity in the second portion of the floating gate.

Abstract: A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. An etch stop layer is formed over the surface of the substrate and the devices, and an inter level dielectric layer (ILD) is formed over the etch stop layer. An antireflection layer (ARC) is formed over the insulator layer, and a photoresist layer is formed over the insulator layer. The photoresist layer is photolithographically patterned to form first holes therethrough which overlie the interconnect areas. Using the patterned photoresist layer as a mask, second holes which underlie the first holes are etched using Reactive Ion Etching (RIE) through the antireflection layer to the insulator layer. Third holes are etched through the insulator layer down to the etch stop layer.

Abstract: A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step.