Patents by Inventor Yoni Aizik

Yoni Aizik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10725848
    Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Tsvika Kurts, Ki W. Yoon, Michael J. St. Clair, Larisa Novakovsky, Hisham Shafi, William H. Penner, Yoni Aizik, Kevin Safford, Hermann Gartler
  • Publication number: 20200057480
    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Publication number: 20200057481
    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Publication number: 20200012329
    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
    Type: Application
    Filed: August 21, 2019
    Publication date: January 9, 2020
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Patent number: 10429919
    Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Publication number: 20190286223
    Abstract: In one embodiment, an apparatus includes a bulk write circuit to generate a bulk write message to send to a destination agent to cause the destination agent to write data comprising register contents into a plurality of registers, at least some of the plurality of registers comprising non-consecutive registers. The bulk write message may include a first message header, a first chunk header including an address of a first register of a first subset of the plurality of registers, and a first payload portion having the register contents for the first subset of the plurality of registers. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2019
    Publication date: September 19, 2019
    Inventors: Ben Furman, Yoni Aizik, Robert P. Adler, Robert Hesse, Chen Ranel
  • Publication number: 20190243701
    Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Tsvika Kurts, Ki W. Yoon, Michael J. St. Clair, Larisa Novakovsky, Hisham Shafi, William H. Penner, Yoni Aizik, Kevin Safford, Hermann Gartler
  • Patent number: 10372198
    Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
  • Patent number: 10345889
    Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
  • Patent number: 10324519
    Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Yoni Aizik, Doron Rajwan, Gal Leibovich, Nadav Shulman, Hisham Abu Salah
  • Publication number: 20190041944
    Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.
    Type: Application
    Filed: June 20, 2018
    Publication date: February 7, 2019
    Inventors: Hisham Abu Salah, Efraim Rotem, Eliezer Weissmann, Yoni Aizik, Daniel D. Lederman
  • Publication number: 20190004582
    Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
  • Publication number: 20180120924
    Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Application
    Filed: August 4, 2017
    Publication date: May 3, 2018
    Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
  • Patent number: 9864667
    Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
  • Publication number: 20170371399
    Abstract: In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Eliezer Weissmann, Efraim Rotem, Yoni Aizik, Doron Rajwan, Gal Leibovich, Nadav Shulman, Hisham Abu Salah
  • Publication number: 20170371400
    Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 28, 2017
    Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
  • Patent number: 9760160
    Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Hisham Abu Salah, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Gal Leibovich, Yevgeni Sabin, Shay Levy
  • Patent number: 9760158
    Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
  • Patent number: 9684541
    Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Arik Gihon, Efraim Rotem, Paul S. Diefenbaugh, Eric C. Samson, Michael Mishaeli, Yoni Aizik, Chen Ranel
  • Patent number: 9671853
    Abstract: In an embodiment, a processor includes at least one core and energy performance gain (EPG) logic to determine an EPG frequency based on a first value of an EPG. The EPG is based upon energy consumed by the processor and upon performance of the processor. The processor also includes a clock generator to generate a frequency of operation of the at least one core based on the EPG frequency. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: Yoni Aizik, Eliezer Weissmann, Efraim Rotem, Yevgeni Sabin, Doron Rajwan, Ahmad Yasin