Patents by Inventor Yoni Choukroun
Yoni Choukroun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260119957Abstract: Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.Type: ApplicationFiled: January 16, 2024Publication date: April 30, 2026Applicant: Ramot at Tel-Aviv University Ltd.Inventors: Yoni CHOUKROUN, Lior WOLF
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Publication number: 20250286564Abstract: The invention presents a universal foundation model for decoding error correction codes (ECC) and a learning-based method for linear block ECCs. The foundation model is trained on multiple codes using a code-invariant embedding, relative positional encoding from derived from parity-check matrices, and a size-invariant transformation to generate a robust noise prediction. A learned distance embedding derived from each code's Tanner graph modulates self-attention, allowing the system to handle both seen and unseen codes without retraining. Overall, this approach replaces specialized, code-specific decoders with a single efficient model, enabling more robust and scalable decoding of diverse error correction codes. The linear block learning component based on the Transformer architecture allows the differentiable training of the code via the Tanner graph connectivity derivation from the parity check matrix, and enables the effective and differentiable joint optimization of the code and of the neural decoder.Type: ApplicationFiled: March 6, 2025Publication date: September 11, 2025Applicant: Ramot at Tel-Aviv University Ltd.Inventors: Yoni CHOUKROUN, Lior WOLF
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Patent number: 12294387Abstract: Disclosed herein are systems and method for training neural network based decoders for decoding error correction codes, comprising obtaining a plurality of training samples comprising one or more codewords encoded using an error correction code and transmitted over a transmission channel where the training samples are subject to gradual interference over a plurality of time steps and associate the encoded codeword(s) with an interference level and a parity check syndrome at each of the plurality of time steps, using the training samples to train a neural network based decoder to decode codewords encoded using an error correction code by (1) estimating a multiplicative interference included in the encoded codeword(s) based on reverse diffusion applied to the encoded codeword(s) across the time steps, (2) computing an additive interference included in the encoded codewords based on the multiplicative interference, and (3) recovering the codeword(s) by removing the additive interference.Type: GrantFiled: July 18, 2023Date of Patent: May 6, 2025Assignee: Ramot at Tel-Aviv University Ltd.Inventors: Yoni Choukroun, Lior Wolf
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Patent number: 12260248Abstract: A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.Type: GrantFiled: February 25, 2020Date of Patent: March 25, 2025Assignee: Huawei Technologies Co., Ltd.Inventors: Tal Horowitz, Uri Weiser, Zuguang Wu, Huibin Luo, Yoni Choukroun
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Publication number: 20240039559Abstract: Disclosed herein are systems and method for training neural network based decoders for decoding error correction codes, comprising obtaining a plurality of training samples comprising one or more codewords encoded using an error correction code and transmitted over a transmission channel where the training samples are subject to gradual interference over a plurality of time steps and associate the encoded codeword(s) with an interference level and a parity check syndrome at each of the plurality of time steps, using the training samples to train a neural network based decoder to decode codewords encoded using an error correction code by (1) estimating a multiplicative interference included in the encoded codeword(s) based on reverse diffusion applied to the encoded codeword(s) across the time steps, (2) computing an additive interference included in the encoded codewords based on the multiplicative interference, and (3) recovering the codeword(s) by removing the additive interference.Type: ApplicationFiled: July 18, 2023Publication date: February 1, 2024Applicant: Ramot at Tel-Aviv University Ltd.Inventors: Yoni CHOUKROUN, Lior WOLF
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Patent number: 11343650Abstract: An unconstrained saddle point of a function is obtained by computing a combination of a first subspace for minimization, and a second subspace for maximization. A combination of a current location including a first and second current location within the first and second subspace is iteratively selected. From the current location, a combination of a step-size including a first and second step-size along a first and second direction of the first and second subspace, is computed. The first and second step-size is to a next first and second location within the first and second subspace. The current location is set to a next location including the next first and second location. The combination of the first and second subspace is according to the next location. The iterations terminate when the next location meets a requirement denoting the unconstrained saddle point. The location indicating the unconstrained saddle point is provided.Type: GrantFiled: December 23, 2020Date of Patent: May 24, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Yoni Choukroun, Michael Zibulevsky
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Patent number: 10878569Abstract: There is provided a method for training a deep convolutional neural network (CNN) for detecting an indication of likelihood of abnormality, comprising: receiving anatomical training images, each including an associated annotation indicative of abnormality for the whole image without an indication of location of the abnormality, executing, for each anatomical training image: decomposing the anatomical training image into patches, computing a feature representation of each patch, computing for each patch, according to the feature representation of the patch, a probability that the patch includes an indication of abnormality, setting a probability indicative of likelihood of abnormality in the anatomical image according to the maximal probability value computed for one patch, and training a deep CNN for detecting an indication of likelihood of abnormality in a target anatomical image according to the patches of the anatomical training images, the one patch, and the probability set for each respective anatomicalType: GrantFiled: March 28, 2018Date of Patent: December 29, 2020Assignee: International Business Machines CorporationInventors: Ayelet Akselrod-Ballin, Ran Bakalo, Rami Ben-Ari, Yoni Choukroun, Pavel Kisilev
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Patent number: 10735141Abstract: A system for reducing analog noise in a noisy channel, comprising: an interface configured to receive analog channel output comprising a stream of noisy binary codewords of a linear code; and a computation component configured to perform the following: for each analog segment of the analog channel output of block length: calculating an absolute value representation and a sign representation of a respective analog segment, calculating a multiplication of a binary representation of the sign representation with a parity matrix of the linear code, inputting the absolute value representation and the outcome of the multiplication into a neural network for acquiring a neural network output, and estimating a binary codeword by component-wise multiplication of the neural network output and the sign representation.Type: GrantFiled: December 21, 2018Date of Patent: August 4, 2020Assignee: Huawei Technologies Co., Ltd.Inventors: Amir Bennatan, Yoni Choukroun, Pavel Kisilev, Junqiang Shen
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Publication number: 20200204299Abstract: A system for reducing analog noise in a noisy channel, comprising: an interface configured to receive analog channel output comprising a stream of noisy binary codewords of a linear code; and a computation component configured to perform the following: for each analog segment of the analog channel output of block length: calculating an absolute value representation and a sign representation of a respective analog segment, calculating a multiplication of a binary representation of the sign representation with a parity matrix of the linear code, inputting the absolute value representation and the outcome of the multiplication into a neural network for acquiring a neural network output, and estimating a binary codeword by component-wise multiplication of the neural network output and the sign representation.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: Amir BENNATAN, Yoni CHOUKROUN, Pavel KISILEV, Junqiang SHEN
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Publication number: 20200192701Abstract: A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Inventors: Tal HOROWITZ, Uri WEISER, Zuguang WU, Huibin LUO, Yoni CHOUKROUN
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Publication number: 20190304092Abstract: There is provided a method for training a deep convolutional neural network (CNN) for detecting an indication of likelihood of abnormality, comprising: receiving anatomical training images, each including an associated annotation indicative of abnormality for the whole image without an indication of location of the abnormality, executing, for each anatomical training image: decomposing the anatomical training image into patches, computing a feature representation of each patch, computing for each patch, according to the feature representation of the patch, a probability that the patch includes an indication of abnormality, setting a probability indicative of likelihood of abnormality in the anatomical image according to the maximal probability value computed for one patch, and training a deep CNN for detecting an indication of likelihood of abnormality in a target anatomical image according to the patches of the anatomical training images, the one patch, and the probability set for each respective anatomicalType: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Ayelet Akselrod-Ballin, Ran Bakalo, Rami Ben-Ari, Yoni Choukroun, Pavel Kisilev