Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

Abstract: A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.

Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

Abstract: Disclosed are an LED driving integrated circuit and a driving method therefor. The LED driving integrated circuit of the present invention relates to a multi-channel AC direct-type LED driving circuit, comprising: an LED array comprising first to k-th (an integer not less than 2) LED groups connected in series; a control unit comprising a plurality of (not less than 2) switches connected to the LED array and a switch control circuit for selectively opening and closing the switches; and a valley-fill circuit, which receives the rectified voltage of an alternating current (AC) voltage, for supplying first and second variant rectified voltages to the LED array. The valley fill circuit supplies the first variant rectified voltage to an input of the first LED group of the LED array, and supplies the second variant rectified voltage to any one of the inputs of the remaining LED groups except the first LED group.

Abstract: A driving circuit for Liquid Crystal Display (LCD) device includes a unity-gain operation amplifier (OP amp), three switches, and two capacitors. The unity-gain OP amp buffers and carries a signal voltage on a transmission line. The first switch switches a connection between a noninverting terminal of the unity-gain OP amp and an input line of the signal voltage. One end of the second switch is connected to the input line of the signal voltage. One end of the third switch is connected to the noninverting terminal of the unity-gain OP amp. The first capacitor is connected between the other end of the third switch and the other end of the second switch. The second capacitor is connected between the other end of the first capacitor and the ground voltage terminal.

Abstract: There is provided a differential current driving current type transmission system. The system includes a transmission line pair for transmitting a signal by a differential scheme; a transmission unit having a transmission circuit for making the transmission line pair have a current difference according to a logic value of a transmission signal and equalizing the transmission line pair at a predetermined timing, and a transmission controller for controlling the signal transmission of the transmission circuit and the equalization of the transmission line pair; and a receiving unit having an I-V converter circuit for mirroring a current difference of the transmission line pair and converting the current difference into a voltage difference, and a differential amplifier for amplifying the voltage difference of the I-V converter circuit.

Abstract: A digital-to-analog converter (DAC) can minimize the increase of an area caused by increase of number of bits. The DAC includes a coarse resistor-string digital-to-analog conversion unit for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2, a fine resistor-string digital-to-analog conversion unit for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, wherein the 2N-level analog voltages is obtained by dividing a level of unit voltage of the coarse resistor-string digital-to-analog conversion unit into 2N-levels, and a voltage combining unit for outputting 22N-level analog output signals by combining the output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to-analog conversion unit.

Abstract: A TFT-LCD source driver for driving L channels of a liquid crystal panel (where L is a positive integer), the TFT-LCD source driver comprising a plurality of DACs (digital-to-analog converters) for converting (M+N)-bit different digital signals into analog signals (where M and N are positive integers), the DAC including: a coarse gradation voltage generator, configured with 2M resistors connected in series, for generating 2M gradation voltages; a first decoder for selecting two consecutive voltages among the 2M gradation voltages in response to M-bit digital signals; a fine gradation voltage generator, configured with 2N resistors connected in series, for receiving output voltages of the first decoder and outputting 2N gradation voltages; and a second decoder for selecting one of the 2N gradation voltages in response to the N-bit digital signals and outputting the selected gradation voltage as the analog signal.

Abstract: A digital-to-analog converter (DAC) can minimize the increase of an area caused by increase of number of bits. The DAC includes a coarse resistor-string digital-to-analog conversion unit for selectively outputting 2N-level analog voltages in response to upper N-bit digital data, wherein N is a natural number greater than or equal to 2, a fine resistor-string digital-to-analog conversion unit for selectively outputting 2N-level analog voltages in response to lower N-bit digital data, wherein the 2N-level analog voltages is obtained by dividing a level of unit voltage of the coarse resistor-string digital-to-analog conversion unit into 2N-levels, and a voltage combining unit for outputting 22N-level analog output signals by combining the output of the coarse resistor-string digital-to-analog conversion unit and the output of the fine resistor-string digital-to-analog conversion unit.

Abstract: There is provided a differential current driving current type transmission system. The system includes a transmission line pair for transmitting a signal by a differential scheme; a transmission unit having a transmission circuit for making the transmission line pair have a current difference according to a logic value of a transmission signal and equalizing the transmission line pair at a predetermined timing, and a transmission controller for controlling the signal transmission of the transmission circuit and the equalization of the transmission line pair; and a receiving unit having an I-V converter circuit for mirroring a current difference of the transmission line pair and converting the current difference into a voltage difference, and a differential amplifier for amplifying the voltage difference of the I-V converter circuit.