Patents by Inventor Yoo-Chul Kong
Yoo-Chul Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10410839Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.Type: GrantFiled: May 26, 2017Date of Patent: September 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yil-Hyung Lee, Yoo-Chul Kong, Jong-Kyu Kim, Seok-Woo Nam, Jong-Soon Park, Kyoung-Sub Shin
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Publication number: 20190272979Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Yil-Hyung Lee, Yoo-Chul Kong, Jong-Kyu Kim, Seok-Woo Nam, Jong-Soon Park, Kyoung-Sub Shin
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Publication number: 20180197719Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.Type: ApplicationFiled: May 26, 2017Publication date: July 12, 2018Inventors: Yil-Hyung Lee, Yoo-Chul Kong, Jong-Kyu Kim, Seok-Woo Nam, Jong-Soon Park, Kyoung-Sub Shin
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Patent number: 9905754Abstract: In a method of forming a pattern of a semiconductor device, a first mask layer and an anti-reflective coating layer may be sequentially formed on a substrate. A photoresist layer may be formed on the anti-reflective coating layer. The photoresist layer may be exposed and developed to form a first preliminary photoresist pattern. A first ion beam etching process may be performed on the first preliminary photoresist pattern to form a second preliminary photoresist pattern. A second ion beam etching process may be performed on the second preliminary photoresist pattern to form a photoresist pattern. A second incident angle of an ion beam in the second ion beam etching process may be greater than a first incident angle of an ion beam in the first ion beam etching process. The anti-reflective coating layer and the first mask layer may be etched using the photoresist pattern as an etching mask to form a mask structure.Type: GrantFiled: June 22, 2017Date of Patent: February 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Ji Yoon, Yoo-Chul Kong, Jong-Kyu Kim, Sang-Kuk Kim, Yil-Hyung Lee
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Patent number: 9899404Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.Type: GrantFiled: December 2, 2015Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyuk Yoo, Dae-Hyun Jang, Yoo-Chul Kong, Kyoung-Sub Shin
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Publication number: 20180006219Abstract: In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.Type: ApplicationFiled: January 25, 2017Publication date: January 4, 2018Inventors: Jae-Hun SEO, Jung-Ik OH, Yoo-Chul KONG, Woo-Ram KIM, Jong-Chul PARK, Gwang-Hyun BAEK, Bok-Yeon WON, Hye-Jin CHOI
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Publication number: 20160111431Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.Type: ApplicationFiled: December 2, 2015Publication date: April 21, 2016Inventors: Jin-Hyuk Yoo, Dae-Hyun Jang, Yoo-Chul Kong, Kyoung-Sub Shin
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Patent number: 9214409Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.Type: GrantFiled: March 6, 2013Date of Patent: December 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyuk Yoo, Dae-Hyun Jang, Yoo-Chul Kong, Kyoung-Sub Shin
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Patent number: 8815676Abstract: Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.Type: GrantFiled: November 8, 2012Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Ryol Yang, Yoo-Chul Kong, Jung-Ho Kim, Jin-Gyun Kim, Jae-Jin Shin, Ji-Hoon Choi
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Publication number: 20130320486Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.Type: ApplicationFiled: March 6, 2013Publication date: December 5, 2013Inventors: Jin-Hyuk YOO, Dae-hyun Jang, Yoo-Chul Kong, Kyoung-Sub Shin
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Patent number: 8557661Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.Type: GrantFiled: December 8, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Han-Geun Yu, Gyung-Jin Min, Seong-Soo Lee, Suk-Ho Joo, Yoo-Chul Kong, Dae-Hyun Jang
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Publication number: 20130065369Abstract: Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.Type: ApplicationFiled: November 8, 2012Publication date: March 14, 2013Inventors: Sang-Ryol Yang, Yoo-Chul Kong, Jung-Ho Kim, Jin-Gyun Kim, Jae-Jin Shin, Ji-Hoon Choi
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Publication number: 20120329224Abstract: A method of forming a fine pattern and a method of manufacturing a semiconductor device. The method of forming a fine pattern includes: forming a hard mask layer on a to-be-etched layer; forming on the hard mask layer a first mask pattern including a plurality of elongated openings that are arranged at predetermined intervals in a first direction and a second direction different from the first direction and are offset from each other in adjacent columns in the second direction; forming on the hard mask layer a second mask pattern including at least two linear openings that each pass through the elongated openings in the adjacent columns and extend in the first direction; forming a hard mask pattern by etching the hard mask layer by using the second mask pattern as an etch mask; and etching the to-be-etched layer by using the hard mask pattern.Type: ApplicationFiled: June 13, 2012Publication date: December 27, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo-chul Kong, Jin-kwan Lee, Gyung-jin Min, Seong-soo Lee
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Patent number: 8309405Abstract: Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.Type: GrantFiled: September 8, 2011Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Ryol Yang, Yoo-Chul Kong, Jin-Gyun Kim, Jae-Jin Shin, Jung-Ho Kim, Ji-Hoon Choi
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Publication number: 20120187471Abstract: A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.Type: ApplicationFiled: December 8, 2011Publication date: July 26, 2012Inventors: Han-Geun YU, Gyung-Jin MIN, Seong-Soo LEE, Suk-Ho JOO, Yoo-Chul KONG, Dae-Hyun JANG
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Publication number: 20120083077Abstract: Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.Type: ApplicationFiled: September 8, 2011Publication date: April 5, 2012Inventors: Sang-Ryol Yang, Yoo-Chul Kong, Jin-Gyun Kim, Jae-Jin Shin, Jung-Ho Kim, Ji-Hoon Choi
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Publication number: 20080061352Abstract: A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.Type: ApplicationFiled: November 5, 2007Publication date: March 13, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doo-Young LEE, Yoo-Chul KONG, Jong-Chul PARK, Sang-Sup JEONG
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Patent number: 7312117Abstract: A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.Type: GrantFiled: July 28, 2005Date of Patent: December 25, 2007Assignee: Samsung Eletronics Co., Ltd.Inventors: Doo-Young Lee, Yoo-Chul Kong, Jong-Chul Park, Sang-Sup Jeong
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Publication number: 20060022256Abstract: A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.Type: ApplicationFiled: July 28, 2005Publication date: February 2, 2006Inventors: Doo-Young Lee, Yoo-Chul Kong, Jong-Chul Park, Sang-Sup Jeong