Abstract: A semiconductor device includes a data input/output control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the data input/output control block suitable for generating a control signal using the first and second voltages, a data input/output block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the data input/output block suitable for inputting and outputting a data signal using the first and second voltages based on the control signal, and a memory block, coupled to the data input/output block, suitable for writing or reading the data signal.

Abstract: An apparatus for protecting a device of a motor drive inverter includes a plurality of power modules configured to control the multi-phase alternating current supplied to the motor. Each of the plurality of power modules includes a top phase switching device connected to a positive terminal of the battery, a bottom phase switching device connected in series to the top phase switching device and connected to a negative terminal of the battery, and a current interruption unit connected in series to the top phase switching device and the bottom phase switching device, and configured to be disconnected when a current greater than or equal to a desired interrupting current flows thereto, so as to prevent a switching device of a power module from being burned out due to an overcurrent by installing a fuse wire to the power module.

Abstract: An overcurrent detection reference compensation system of a switching element for an inverter and an overcurrent detection system using the same can correct an overcurrent detection reference used to detect an overcurrent of a switching element according to a temperature of the switching element.

Abstract: A semiconductor device includes a drive control circuit and a write control circuit. The drive control circuit generates a pre-drive control signal and a drive control signal based on a latch command and generates a pattern drive control signal based on a pattern latch command. The write control circuit stores drive data generated from data inputted based on the pre-drive control signal and the drive control signal or stores the drive data driven to a predetermined logic level based on the pattern drive control signal.

Abstract: A semiconductor device includes a power gating control block and a power gating circuit. The power gating control block activates a data power control signal during a period that is set by a target code, the period being from a point in time in which the semiconductor device enters a read mode or a write mode. In addition, the power gating control block deactivates an operation power control signal in a power-down mode. The power gating circuit inhibits a data power signal from being supplied to a data input/output block based on the data power control signal. Moreover, the power gating control block inhibits an operation power signal from being supplied to an internal operation control block based on the operation power control signal.

Abstract: A semiconductor device includes a drive control circuit and a write control circuit. The drive control circuit generates a pre-drive control signal and a drive control signal based on a latch command and generates a pattern drive control signal based on a pattern latch command. The write control circuit stores drive data generated from data inputted based on the pre-drive control signal and the drive control signal or stores the drive data driven to a predetermined logic level based on the pattern drive control signal.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first pad region located at a first region of the first semiconductor chip and a second pad region located at a second region of the first semiconductor chip. The second semiconductor chip has a third pad region located at a first region of the second semiconductor chip and a fourth pad region located at a second region of the second semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip to be offset in a first lateral direction relative to the first semiconductor chip.

Abstract: A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.

Abstract: A power gating circuit is provided. The power gating circuit includes a logic gate group. The power gating circuit also includes a first switching circuit coupled to first and second supply voltages and the logic gate group. The power gating circuit further includes a second switching circuit coupled to the first and second supply voltages and the logic gate group. The first and second supply voltages are supplied to the logic gate group through the first switching circuit based on a voltage select signal. The first and second supply voltages are supplied to the logic gate group through the second switching circuit based on the voltage select signal and a power down signal.

Abstract: A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.

Abstract: Disclosed is an apparatus for forming an electronic material layer, in which charged particles damaging the electronic material layer are prevented from arriving at a substrate but processing gas ions maximizing activation of the electronic material layer are accelerated and passed while the electronic material layer is formed on the substrate or the substrate having a functional layer thereon by sputtering, thereby forming the electronic material layer having good electrical/physical characteristics at room temperature.