Patents by Inventor Yoo-Sang Hwang

Yoo-Sang Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10665498
    Abstract: A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Jung Kim, Bong-Soo Kim, Yong-Kwan Kim, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 10629600
    Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-jung Kim, Sung-hee Han, Ki-seok Lee, Bong-soo Kim, Yoo-sang Hwang
  • Patent number: 10600646
    Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming an amorphous transition metal oxide structure on a substrate and replacing the amorphous transition metal oxide structure by a transition metal dichalcogenide structure. The transition metal dichalcogenide structure includes atomic layers, that are substantially parallel to a surface of the transition metal dichalcogenide structure.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-jin Park, Bong-soo Kim, Jin-bum Kim, Yoo-sang Hwang
  • Patent number: 10580876
    Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-hyeok Ahn, Eun-jung Kim, Hui-jung Kim, Ki-seok Lee, Bong-soo Kim, Myeong-dong Lee, Sung-hee Han, Yoo-sang Hwang
  • Patent number: 10573652
    Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myeong-Dong Lee, Jun-Won Lee, Ki Seok Lee, Bong-Soo Kim, Seok Han Park, Sung Hee Han, Yoo Sang Hwang
  • Publication number: 20200035541
    Abstract: A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.
    Type: Application
    Filed: January 28, 2019
    Publication date: January 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-hwan Chun, Hui-jung KIM, Keun-nam KIM, Sung-hee HAN, Yoo-sang HWANG
  • Patent number: 10515798
    Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: December 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-jin Park, Bong-soo Kim, Jin-bum Kim, Yoo-sang Hwang
  • Patent number: 10510759
    Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hui-jung Kim, Bong-soo Kim, Sung-hee Han, Yoo-sang Hwang
  • Publication number: 20190362791
    Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-woo KIM, Jae-kyu LEE, Ki-seok SUH, Hyeong-sun HONG, Yoo-sang HWANG, Gwan-hyeob KOH
  • Patent number: 10468103
    Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-woo Kim, Jae-kyu Lee, Ki-seok Suh, Hyeong-sun Hong, Yoo-sang Hwang, Gwan-hyeob Koh
  • Publication number: 20190214293
    Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 11, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyu Jin Kim, Min Su Choi, Sung Hee Han, Bong Soo Kim, Yoo Sang Hwang
  • Patent number: 10332831
    Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Augustin Jinwoo Hong, Dae-Ik Kim, Chan-Sic Yoon, Ki-Seok Lee, Dong-Min Han, Sung-Ho Jang, Yoo-Sang Hwang, Bong-Soo Kim, Je-Min Park
  • Publication number: 20190189617
    Abstract: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.
    Type: Application
    Filed: June 21, 2018
    Publication date: June 20, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hui-jung KIM, Sung-hee Han, Ki-seok Lee, Bong-soo Kim, Yoo-sang Hwang
  • Publication number: 20190164976
    Abstract: A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.
    Type: Application
    Filed: June 11, 2018
    Publication date: May 30, 2019
    Inventors: Hui-jung Kim, Bong-soo Kim, Sung-hee Han, Yoo-sang Hwang
  • Publication number: 20190157275
    Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.
    Type: Application
    Filed: September 18, 2018
    Publication date: May 23, 2019
    Inventors: Ki-Seok Lee, Bomg-Soo Kim, Ji-Young Kim, Sung-Hee Han, Yoo-Sang Hwang
  • Publication number: 20190096890
    Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.
    Type: Application
    Filed: April 4, 2018
    Publication date: March 28, 2019
    Inventors: MYEONG-DONG LEE, JUN-WON LEE, KI SEOK LEE, BONG-SOO KIM, SEOK HAN PARK, SUNG HEE HAN, YOO SANG HWANG
  • Publication number: 20190097007
    Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.
    Type: Application
    Filed: March 7, 2018
    Publication date: March 28, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-hyeok AHN, Eun-jung Kim, Hui-jung Kim, Ki-seok Lee, Bong-soo Kim, Myeong-dong Lee, Sung-hee Han, Yoo-sang Hwang
  • Publication number: 20190074180
    Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-jin PARK, Bong-soo Kim, Jin-bum Kim, Yoo-sang Hwang
  • Publication number: 20190074380
    Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-jin PARK, Jin-bum Kim, Bong-soo Kim, Kyu-pil Lee, Hyeong-sun Hong, Yoo-sang Hwang
  • Publication number: 20190074179
    Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming an amorphous transition metal oxide structure on a substrate and replacing the amorphous transition metal oxide structure by a transition metal dichalcogenide structure. The transition metal dichalcogenide structure includes atomic layers, that are substantially parallel to a surface of the transition metal dichalcogenide structure.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-jin PARK, Bong-soo KIM, Jin-bum KIM, Yoo-sang HWANG