Patents by Inventor Yoo-seok Jang

Yoo-seok Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240149322
    Abstract: According to an exemplary embodiment of the present disclosure, disclosed is an aluminum coated blank that includes a first coated steel sheet; a second coated steel sheet connected to the first coated steel sheet; and a joint portion that connects the first coated steel sheet to the second coated steel plate at a boundary between the first coated steel sheet and the second coated steel sheet.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 9, 2024
    Inventors: Chang Yong Lee, Sung Ryul Kim, Jeong Seok Kim, Joo Sik Hyun, Yoo Dong Chung, Soon Geun Jang
  • Patent number: 11975375
    Abstract: According to an exemplary embodiment of the present disclosure, disclosed is an aluminum coated blank that includes a first coated steel sheet; a second coated steel sheet connected to the first coated steel sheet; and a joint portion that connects the first coated steel sheet to the second coated steel plate at a boundary between the first coated steel sheet and the second coated steel sheet.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 7, 2024
    Assignee: Hyundai Steel Company
    Inventors: Chang Yong Lee, Sung Ryul Kim, Jeong Seok Kim, Joo Sik Hyun, Yoo Dong Chung, Soon Geun Jang
  • Publication number: 20230368733
    Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 16, 2023
    Inventors: Yoon Jung CHAI, Won Jun LEE, Chol Ho KIM, Sung Hoon LIM, Yoo Seok JANG
  • Patent number: 11749195
    Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoon Jung Chai, Won Jun Lee, Chol Ho Kim, Sung Hoon Lim, Yoo Seok Jang
  • Publication number: 20230186849
    Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.
    Type: Application
    Filed: June 29, 2022
    Publication date: June 15, 2023
    Inventors: Yoon Jung CHAI, Won Jun LEE, Chol Ho KIM, Sung Hoon LIM, Yoo Seok JANG
  • Publication number: 20220199690
    Abstract: A display device is provided. A display device including a plurality of light-output areas through which incident light is emitted and a light-blocking area which blocks the incident light, the display device includes a substrate, a bank layer which is disposed in the light-blocking area on the substrate and defines a plurality of openings, each of which is disposed in one of the plurality of light-output areas, and a color control pattern disposed in the opening of the bank layer, wherein the bank layer includes a first bank area which has a first thickness and defines the plurality of openings and a second bank area which is disposed between the plurality of openings and has a second thickness smaller than the first thickness.
    Type: Application
    Filed: September 23, 2021
    Publication date: June 23, 2022
    Inventors: Seon Uk LEE, Hwa Yeul OH, Seung Kil YANG, Song Ee LEE, Yoo Seok JANG, Jeong Ki KIM, Jong Hoon KIM, Ju Yong KIM, Ji Seong YANG, Jun Hwi LIM, Sang Yeon Hwang
  • Patent number: 9892983
    Abstract: An apparatus and method of forming an epitaxial layer are provided. The apparatus includes a process chamber in which an epitaxial process is performed to form epitaxial layer on a substrate. A first supplier supplies source gases for the epitaxial layer into the process chamber. A second supplier supplies dopants into the process chamber. A detector detects a composition ratio of the epitaxial layer and a concentration of the dopants in the epitaxial layer during the epitaxial growth process. And a controller controls a mass flow of at least one of the source gases and a mass flow of the dopants in-line with the epitaxial growth process. Accordingly, the layer thickness of the epitaxial layer can be accurately controlled in real time in line with the epitaxial process.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Kook Kim, Bang-Won Kim, Yu-Sin Yang, Young-Jee Yoon, Sang-Kil Lee, Yoo-Seok Jang, Chung-Sam Jun
  • Publication number: 20160181167
    Abstract: An apparatus and method of forming an epitaxial layer are provided. The apparatus includes a process chamber in which an epitaxial process is performed to form epitaxial layer on a substrate. A first supplier supplies source gases for the epitaxial layer into the process chamber. A second supplier supplies dopants into the process chamber. A detector detects a composition ratio of the epitaxial layer and a concentration of the dopants in the epitaxial layer during the epitaxial growth process. And a controller controls a mass flow of at least one of the source gases and a mass flow of the dopants in-line with the epitaxial growth process. Accordingly, the layer thickness of the epitaxial layer can be accurately controlled in real time in line with the epitaxial process.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 23, 2016
    Inventors: Min-Kook KIM, Bang-Won KIM, Yu-Sin YANG, Young-Jee YOON, Sang-Kil LEE, Yoo-Seok JANG, Chung-Sam JUN
  • Patent number: 7194325
    Abstract: A system to and method of monitoring a condition of a process tool. The system monitors a condition of a process tool to correctly detect a faulty operation or malfunction of the process tool. The system to monitor the condition of the process tool includes a first model storage unit to store one or more good models generated by data associated with the process tool, a second model storage unit to store one or more faulty models generated by the data associated with the process tool, a model selector to receive tool data from the process tool, and to select one of the good models and one of the faulty models in association with the received tool data, and an error detector to receive process data from the process tool, to compare the received process data with the good and faulty models selected by the model selector, and to estimate a condition of the process tool.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: March 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Jun Lee, Seung Yong Doh, Chung Hun Park, Yoo Seok Jang
  • Patent number: 7184910
    Abstract: A method of compensating sensor data and a method of evaluating an interlock of an interlock system, in which an allowable variation between sensors varying depending on a driving time for a set of equipment, an RF time, the number of wafers, etc. is minimized, thereby enhancing detection reliability of a defective wafer.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: February 27, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-jun Lee, Hak-yong Kim, Yoo-seok Jang, Chang-hun Park, Seung-Yong Doh
  • Publication number: 20060086172
    Abstract: A method of compensating sensor data used in an interlock system comprises setting a predetermined drift upper limit and a predetermined drift lower limit, creating a reference pattern information about a reference model, creating a sensor pattern information about the sensor data, determining whether the sensor pattern information satisfies the drift upper limit and the drift lower limit, calculating a drift offset according to the reference pattern information and the sensor pattern information when the sensor pattern information satisfies the drift upper limit and the drift lower limit, and compensating the sensor data according to the calculated drift offset.
    Type: Application
    Filed: August 4, 2005
    Publication date: April 27, 2006
    Inventors: Seung-jun Lee, Hak-yong Kim, Yoo-seok Jang, Chang-hun Park, Seung-Yong Doh