Abstract: The present disclosure relates to an OLED that includes a first electrode; a second electrode facing the first electrode; a first emitting material layer including a first host, a second host and a blue dopant and positioned between the first and second electrodes; a first electron blocking layer including an electron blocking material of a spirofluorene-substituted amine derivative and positioned between the first electrode and the first emitting material layer; and a first hole blocking layer including a first hole blocking material of an azine derivative and positioned between the second electrode and the first emitting material layer, wherein the first host is an anthracene derivative, and the second host is a deuterated anthracene derivative.

Abstract: A processor-implemented method includes generating a preprocessed infrared (IR) image by performing first preprocessing based on an IR image including an object; generating a preprocessed depth image by performing second preprocessing based on a depth image including the object; and determining whether the object is a genuine object based on the preprocessed IR image and the preprocessed depth image

Abstract: The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device of the present disclosure shows high luminous efficiency and good lifespan by comprising a specific combination of the plural kinds of host compounds and a specific hole transport compound.

Abstract: Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

Abstract: Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

Abstract: A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film defining the active region and including a second gate-trench formed when a gate region is etched to a second depth, a gate buried below the first gate trench and the second gate trench, and a source plug and a drain plug formed when a conductive material is deposited in a source region and a drain region of the active region.

Abstract: A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film defining the active region and including a second gate-trench formed when a gate region is etched to a second depth, a gate buried below the first gate trench and the second gate trench, and a source plug and a drain plug formed when a conductive material is deposited in a source region and a drain region of the active region.

Abstract: A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film defining the active region and including a second gate-trench formed when a gate region is etched to a second depth, a gate buried below the first gate trench and the second gate trench, and a source plug and a drain plug formed when a conductive material is deposited in a source region and a drain region of the active region.

Abstract: A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film defining the active region and including a second gate-trench formed when a gate region is etched to a second depth, a gate buried below the first gate trench and the second gate trench, and a source plug and a drain plug formed when a conductive material is deposited in a source region and a drain region of the active region.

Abstract: A pseudonoise code teaching loop (PNCTL) measures the difference in energy between a smart antenna array output that is despread using an early pseudonoise code and a late pseudonoise code and contains a chip time shifting current based on this difference. Using multiple elements of the array significantly improves performance.

Abstract: A fabricating method of a capacitor is disclosed. Particularly, a fabricating method of a capacitor which forms a capacitor in the place where the insulation layer of an STI region is removed, preventing interlayer dielectric layers from becoming thick. A disclosed method comprises: defining an STI region in the predetermined region of a substrate; removing the insulation layer of the STI region where a capacitor will be formed; forming a gate insulation layer and a first polysilicon layer on the substrate, and patterning the first polysilicon layer; and forming a first insulation layer and a second polysilicon layer on the substrate, and patterning the first insulation layer and the second polysilicon layer.

Abstract: A bipolar transistor and method of fabricating the same is disclosed. Particularly, a bipolar transistor may have an emitter and a collector diffusion layer in the sidewalls and the bottom of a device isolation trench. A method includes the steps of: forming a device isolation trench in a substrate; forming a photoresist pattern and implanting ions into the sidewalls and the bottom of the trench to form an emitter and a collector; removing the photoresist pattern; and filling the trench with an insulation layer to form the device isolation structure. Accordingly, the transistor and method can minimize device area by forming the diffusion layer of an emitter and a collector in the sidewalls and the bottom of the trench, and can provide a deep impurity diffusion layer without a high temperature diffusion process. In addition, the transistor and method can provide both a high amplification factor and a high current driving force.