Patents by Inventor Yoo Cheol Shin
Yoo Cheol Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936318Abstract: Charging system and method using a motor driving system are proposed. The charging system includes a battery, an inverter to which D.C. power stored in the battery is applied, including a plurality of legs each including two switching elements, a motor including a plurality of coils of which first ends are respectively connected to connection nodes of the switching elements of each of the plurality of legs, and second ends are connected to each other to form a neutral point, and an inverter driving part configured to control switching of the switching elements, so that switching speeds of the switching elements are different for each mode of a motor driving mode and a charging mode so as to change magnitude of charging voltage supplied to the neutral point of the motor and to output the charging voltage to the battery.Type: GrantFiled: June 1, 2022Date of Patent: March 19, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Ji Woong Jang, Sang Cheol Shin, Yoo Jong Lee, Ki Jong Lee, Ho Tae Chun
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Publication number: 20210175244Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: ApplicationFiled: January 22, 2021Publication date: June 10, 2021Inventors: Yoo-cheol SHIN, Young-woo PARK, Jae-duk LEE
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Patent number: 10903226Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: GrantFiled: April 9, 2020Date of Patent: January 26, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
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Publication number: 20200235119Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: ApplicationFiled: April 9, 2020Publication date: July 23, 2020Inventors: Yoo-cheol SHIN, Young-woo PARK, Jae-duk LEE
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Patent number: 10685708Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.Type: GrantFiled: August 9, 2018Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Chang Hoon Jeon, Yoo Cheol Shin, Jun Hee Lim, Sung Kweon Baek, Chan Ho Lee, Won Chul Jang, Sun Gyung Hwang
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Patent number: 10644019Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: GrantFiled: April 26, 2019Date of Patent: May 5, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
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Publication number: 20190267088Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.Type: ApplicationFiled: August 9, 2018Publication date: August 29, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Chang Hoon JEON, Yoo Cheol Shin, Jun Hee Lim, Sung Kweon Baek, Chan Ho Lee, Won Chul Jang, Sun Gyung Hwang
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Publication number: 20190252401Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
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Patent number: 10381370Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: GrantFiled: January 12, 2018Date of Patent: August 13, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
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Patent number: 10109644Abstract: In one embodiment, the semiconductor device includes a substrate having an impurity region, and the substrate and the impurity region have a different impurity characteristic. The semiconductor device further includes a stack of alternating first interlayer insulating layers and gate electrode layers on the substrate; at least one second interlayer insulating layer formed on the stack; a plurality of bit lines formed on the second interlayer insulating layer; and a first plurality of channel structures formed through the stack on the substrate. The first plurality of channel structures are electrically connected to respective ones of the plurality of bit lines. A second plurality of channel structures are formed through the stack on the impurity region, and the second plurality of channel structures are electrically insulated from the plurality of bit lines.Type: GrantFiled: December 20, 2016Date of Patent: October 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yoo Cheol Shin, Tae Hun Kim
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Publication number: 20180138192Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Inventors: Yoo-cheol SHIN, Young-woo PARK, Jae-duk LEE
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Patent number: 9905570Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: GrantFiled: February 8, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
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Publication number: 20170352680Abstract: In one embodiment, the semiconductor device includes a substrate having an impurity region, and the substrate and the impurity region have a different impurity characteristic. The semiconductor device further includes a stack of alternating first interlayer insulating layers and gate electrode layers on the substrate; at least one second interlayer insulating layer formed on the stack; a plurality of bit lines formed on the second interlayer insulating layer; and a first plurality of channel structures formed through the stack on the substrate. The first plurality of channel structures are electrically connected to respective ones of the plurality of bit lines. A second plurality of channel structures are formed through the stack on the impurity region, and the second plurality of channel structures are electrically insulated from the plurality of bit lines.Type: ApplicationFiled: December 20, 2016Publication date: December 7, 2017Inventors: Yoo Cheol SHIN, Tae Hun KIM
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Patent number: 9431415Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: GrantFiled: November 6, 2014Date of Patent: August 30, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
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Publication number: 20160155751Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: ApplicationFiled: February 8, 2016Publication date: June 2, 2016Inventors: Yoo-cheol SHIN, Young-woo PARK, Jae-duk LEE
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Publication number: 20150129878Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.Type: ApplicationFiled: November 6, 2014Publication date: May 14, 2015Inventors: Yoo-cheol SHIN, Young-woo PARK, Jae-duk LEE
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Patent number: 8575680Abstract: A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.Type: GrantFiled: August 1, 2012Date of Patent: November 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Yoo-Cheol Shin, Joon-Hee Lee
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Publication number: 20130032871Abstract: A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.Type: ApplicationFiled: August 1, 2012Publication date: February 7, 2013Inventors: Yoo-Cheol SHIN, Joon-Hee Lee
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Patent number: 8228738Abstract: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.Type: GrantFiled: December 23, 2010Date of Patent: July 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Tae Park, Jung-Dal Choi, Jong-Sun Sel, Yoo-Cheol Shin
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Patent number: 8218363Abstract: Multilevel flash memory and methods of programming/reading flash memory are disclosed. The multilevel flash memory device comprises a status detector configured to detect whether or not a target memory cell is programmed to an erase state, and a control logic unit controlling a program voltage applied to a neighboring memory cell adjacent to the target memory cell and to be programmed to one of a plurality of standard program states, such that the neighboring memory cell is programmed to a corresponding one of a plurality of correction program states different from the one of the plurality of standard program states.Type: GrantFiled: February 1, 2010Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jaehong Kim, Hong-rak Son, Jun-jin Kong, Yoo-cheol Shin