Abstract: A substrate bias generator which includes: an MOS capacitor having an electrically insulating film located between two electrodes, one of which is disposed on one main face of a P.sup.- semiconductor substrate; and first, second and a third N.sup.+ semiconductor regions disposed in a spaced relationship on that main face. The first and second regions form a grounded source and a drain of an MOSFET having a gate connected to both the drain and the other electrode of the capacitor. The second and third regions form a source and a drain of another MOSFET having a gate connected to both the drain and the other main face of the substrate. A train of square pulses is supplied to the one electrode of the capacitor.