Patents by Inventor Yoo-Jung Lee
Yoo-Jung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143140Abstract: A method of performing chatroom transition, performed by a user terminal is provided. The method may include: continuously displaying, while a screen of a first chatroom that is active is displayed on a user terminal, a first notification bar indicating at least one first new message occurring in a second chatroom; and activating the second chatroom and displaying a screen of the second chatroom, instead of the screen of the first chatroom, in response to a first user input to select the first notification bar.Type: ApplicationFiled: October 27, 2023Publication date: May 2, 2024Applicant: SAMSUNG SDS CO., LTD.Inventors: In Pyo KIM, Mi Geon CHO, Yoo Jung KIM, Da Gun LEE
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Publication number: 20240146823Abstract: A method, which is performed by at least one processor, includes: displaying a currently running application list in response to a first user input; generating a recommended application set including one or more recommended applications for configuring a split screen for a first application included in the currently running application list; displaying the recommended application set for the first application at a position adjacent to the first application; selecting, based on a second user input, a recommended application in the recommended application set for the first application; configuring a split screen including the first application and the selected recommended application; and automatically displaying the split screen.Type: ApplicationFiled: October 26, 2023Publication date: May 2, 2024Applicant: Samsung SDS Co., Ltd.Inventors: Mi Geon CHO, In Pyo Kim, Yoo Jung Kim, Da Gun Lee
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Patent number: 11963364Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.Type: GrantFiled: September 28, 2022Date of Patent: April 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seok Han Park, Yong Seok Kim, Hui-Jung Kim, Satoru Yamada, Kyung Hwan Lee, Jae Ho Hong, Yoo Sang Hwang
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Patent number: 11952412Abstract: The present invention provides a recombinant exosome and uses thereof. More particularly, the present invention provides a recombinant exosome wherein a phagocytosis promoting protein is presented on the surface of the exosome.Type: GrantFiled: April 3, 2022Date of Patent: April 9, 2024Assignee: SHIFTBIOInventors: Eun-ee Koh, Eun Jung Lee, Yoo Soo Yang, In-San Kim
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Publication number: 20220230688Abstract: A memory device includes: a memory cell array including a security region configured to store security data; and a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Yoo-jung Lee, Jang-seok CHOI, Duk-sung KIM, Hyun-joong KIM
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Patent number: 10867690Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.Type: GrantFiled: April 24, 2019Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Joong Kim, Duk-Sung Kim, Yoo-Jung Lee, Jang-Seok Choi
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Publication number: 20200176062Abstract: A memory device includes: a memory cell array including a security region configured to store security data; and a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.Type: ApplicationFiled: August 1, 2019Publication date: June 4, 2020Inventors: Yoo-jung LEE, Jang-seok CHOI, Duk-sung KIM, Hyun-joong KIM
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Publication number: 20200135292Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.Type: ApplicationFiled: April 24, 2019Publication date: April 30, 2020Inventors: Hyun-Joong KIM, Duk-Sung KIM, Yoo-Jung LEE, Jang-Seok CHOI
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Patent number: 9870293Abstract: A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines, and control logic configured to control execution of a post package repair operation by the memory device. The control logic includes a PPR control circuit that programs a bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.Type: GrantFiled: November 8, 2016Date of Patent: January 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Jin Lee, Ju-Yun Jung, Yoo-Jung Lee
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Publication number: 20170185499Abstract: A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines, and control logic configured to control execution of a post package repair operation by the memory device. The control logic includes a PPR control circuit that programs a bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.Type: ApplicationFiled: November 8, 2016Publication date: June 29, 2017Inventors: SEONG-JIN LEE, JU-YUN JUNG, YOO-JUNG LEE
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Publication number: 20170147230Abstract: A memory device includes a first memory having first hardware properties, a second memory having second hardware properties different from the first hardware properties, and a controller configured to receive a signal, representing the first or second hardware properties, with a command to select the first memory or the second memory based on the received signal. The controller controls the selected first or second memory such that an operation according to the command is performed on the selected first or second memory.Type: ApplicationFiled: October 17, 2016Publication date: May 25, 2017Inventors: YOO-JUNG LEE, JU-YUN JUNG, HYUN-JOONG KIM, HA-RYONG YOON
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Patent number: 9543155Abstract: A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.Type: GrantFiled: December 21, 2015Date of Patent: January 10, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Bok-Young Lee, Yoo-Jung Lee, Dong-Hoon Khang, Do-Hyoung Kim, Cheol Kim, In-Hee Lee, Ji-Eun Han
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Publication number: 20160218010Abstract: A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.Type: ApplicationFiled: December 21, 2015Publication date: July 28, 2016Inventors: Bok-Young LEE, Yoo-Jung LEE, Dong-Hoon KHANG, Do-Hyoung KIM, Cheol KIM, In-Hee LEE, Ji-Eun HAN
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Patent number: 9287161Abstract: A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.Type: GrantFiled: September 26, 2014Date of Patent: March 15, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Hyun Lee, Myeong-Cheol Kim, Yoo-Jung Lee, Il-Sup Kim, Seung-Ju Park
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Publication number: 20150140810Abstract: A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.Type: ApplicationFiled: September 26, 2014Publication date: May 21, 2015Inventors: Sang-Hyun LEE, Myeong-Cheol KIM, Yoo-Jung LEE, IL-Sup KIM, Seung-Ju PARK
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Publication number: 20140057427Abstract: Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.Type: ApplicationFiled: November 4, 2013Publication date: February 27, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Kwon KIM, Young-Ju PARK, Dong-Hyuk YEAM, Yoo-jung LEE, Myeong-cheol KIM, Do-Hyoung KIM, Heung-Sik PARK
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Patent number: 8617991Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.Type: GrantFiled: June 19, 2012Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Chan Lee, Yoo-Jung Lee, Ki-Hyung Ko, Dae-Young Kwak, Seung-Jae Lee, Jae-Sung Hur, Sang-Bom Kang, Cheol Kim, Bo-Un Yoon
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Patent number: 8592265Abstract: Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.Type: GrantFiled: September 23, 2011Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Kwon Kim, Young-Ju Park, Dong-Hyuk Yeam, Yoo-Jung Lee, Myeong-Cheol Kim, Do-Hyoung Kim, Heung-Sik Park
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Publication number: 20130012021Abstract: A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.Type: ApplicationFiled: June 19, 2012Publication date: January 10, 2013Inventors: Jung-Chan LEE, Yoo-Jung LEE, Ki-Hyung KO, Dae-Young KWAK, Seung-Jae LEE, Jae-Sung HUR, Sang-Bom KANG, Cheol KIM, Bo-Un YOON
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Patent number: 8228465Abstract: A white phosphor including: 40 to 50 parts by weight of a blue phosphor selected from the group consisting of ZnS:(Ag,Cl), ZnS:(Ag,Al), ZnS:(Ag,Al,Cl), and a combination thereof; 20 to 30 parts by weight of a green phosphor (Sr1-xCax)Ga2S4:Eu (0?x<0.2); and 20 to 30 parts by weight of a red phosphor selected from the group consisting of Y2O3:Eu, Y2O3:(Eu,Tb), Y2O2S:Eu, Y2O2S:(Eu,Tb), and combinations thereof. The white phosphor can be included in a light emission device. The light emission device can be included in a liquid crystal display.Type: GrantFiled: August 27, 2008Date of Patent: July 24, 2012Assignee: Samsung SDI Co., Ltd.Inventors: Yong-Chan You, Jae-Woo Bae, Gyeong-Jae Heo, Kyu-Chan Park, Sang-Hyuk Lee, Sun-Hwa Kwon, Ji-Hyun Kim, Ui-Song Do, Young-Suk Cho, Byung-Kyun Kim, Hui-Young Ku, Yoo-Jung Lee