Abstract: Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.

Abstract: Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the selected memory cell; applying a first pass voltage to non-selected memory cells closest to the selected memory cell of the cell string; applying a second pass voltage to second closest non-selected memory cells to the selected memory cell; and applying a third pass voltage to other non-selected memory cells, where the first pass voltage is less than each of the second and third pass voltages and the second pass voltage is greater than the third pass voltage.

Abstract: Optical waveguide and coupler devices and methods include a trench formed in a bulk semiconductor substrate, for example, a bulk silicon substrate. A bottom cladding layer is formed in the trench, and a core region is formed on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector can be formed under the coupler device and/or the waveguide device. Because the optical devices are integrated in a bulk substrate, they can be readily integrated with other devices on a chip or die in accordance with silicon photonics technology. Specifically, for example, the optical devices can be integrated in a DRAM memory circuit chip die.

Abstract: An image sensor includes a clock signal generator configured to generate and output at least first and second clock signals, a plurality of pixels configured to generate associated distance signals based on corresponding clock signals from among the at least first and second clock signals and light reflected by an object, and a distance information deciding unit configured to determine distance information with respect to the object by using the associated distance signals. At least one first pixel from among the plurality of pixels is configured to generate the associated distance signal based on at least the first clock signal, and at least one second pixel from among the plurality of pixels, which is adjacent to the at least one first pixel, is configured to generate the associated distance signal based on at least the second clock signal.

Abstract: Image sensors include a second photoelectric conversion device disposed in a lower portion of a substrate and a first photoelectric conversion device extending between the secondary photoelectric conversion device and a light receiving surface of the substrate. Electrical isolation between the first and second photoelectric conversion devices is provided by a photoelectron barrier, which may be an optically transparent electrically insulating material. MOS transistors may be utilized to transfer photoelectrons generated within the first and second photoelectric conversion devices to a floating diffusion region within the image sensor. These transistors may represent one example of means for transferring photoelectrons generated in the first and second photoelectric conversion devices to a floating diffusion region in the substrate, in response to first and second gating signals, respectively. The first and second gating signals may be active during non-overlapping time intervals.

Abstract: Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region.

Abstract: The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.

Abstract: A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.

Abstract: Example embodiments include nonvolatile memory devices that have good operation performance and may be made in a highly integrated structure, and methods of operating the same. Example embodiments of the nonvolatile memory devices include a substrate electrode, and a semiconductor channel layer on the substrate electrode, a floating gate electrode on the substrate electrode, wherein a portion of the floating gate electrode faces the semiconductor channel layer, a control gate electrode on the floating gate electrode, and wherein a distance between a portion of the floating gate electrode and the substrate electrode is smaller than a distance between the semiconductor channel layer and the substrate electrode wherein charge tunneling occurs.

Abstract: A pixel of an image sensor, the pixel including a plurality of photoelectric conversion elements arranged in a semiconductor substrate; and a first transfer circuit for sequentially transferring photo-charges generated by each of the plurality of photoelectric conversion elements to a first floating diffusion node.

Abstract: Example embodiments provide a method for programming a resistive memory device that includes a resistance conversion layer. The method may include applying multiple pulses to the resistance conversion layer. The multiple pulses may include at least two pulses, where a magnitude of each pulse of the at least two pulses is the same. A first pulse of the at least two pulses may be applied on one side of the resistance conversion layer and a second pulse of the at least two pulses may be applied on the other side of the resistance conversion layer. The applying step may be performed during a set programming operation or a reset programming operation. A resistive memory device for programming a resistance conversion layer may include a first and second electrode, a lower structure, and the resistance conversion layer coupled between the first and second electrodes.

Abstract: Image sensors include three-dimensional (3D) color image sensors having an array of sensor pixels therein. A 3-D color image sensor may include a 3-D image sensor pixel having a plurality of color sensors and a depth sensor therein. The plurality of color sensors may include red, green and blue sensors extending adjacent the depth sensor. A rejection filter is also provided. This rejection filter, which extends opposite a light receiving surface of the 3-D image sensor pixel, is configured to be selectively transparent to visible and near-infrared light relative to far-infrared light. The depth sensor may also include an infrared filter that is selectively transparent to near-infrared light having wavelengths greater than about 700 nm relative to visible light.

Abstract: An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.

Abstract: A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.

Abstract: A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM includes a gate that contacts the channel layer and the charge reserving layer.

Abstract: Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage.

Abstract: Provided is an image sensor having a depth sensor. The image sensor includes a substrate including a visible light region and a non-visible light region, a first well and a second well having a first conductivity type and in the non-visible light perception region, and a first gate and a second gate configured to receive voltages of opposite phases, respectively, and apply voltages to the first well and the second well, respectively.

Abstract: Provided is a memory module, a system using the memory module, and a method of fabricating the memory module. The memory module may include a printed circuit board and a memory package on the printed circuit board. The printed circuit board may include an embedded optical waveguide and a first optical window extending from the optical waveguide to a first surface of the printed circuit board. The memory package may also include a memory die having an optical input/output section and a second optical window. The optical input/output section, the second optical window, and the first optical window may be arranged in a line and the first optical window and the second optical window may be configured to at least one of transmit an optical signal from the optical waveguide to the optical input/output section and transmit an optical signal from the optical input/output section to the optical waveguide.

Abstract: Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.

Abstract: Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.