Abstract: A multi-socket guide for guiding a semiconductor package to a semiconductor package testing device includes a housing, a guiding unit disposed in the housing, the guiding unit guiding the housing to the semiconductor package testing device, and a mounting unit disposed in the housing, the mounting unit receiving the semiconductor package, wherein a size of the mounting unit corresponds to a size of a ball area of the semiconductor package.

Abstract: A multi-socket guide for guiding a semiconductor package to a semiconductor package testing device includes a housing, a guiding unit disposed in the housing, the guiding unit guiding the housing to the semiconductor package testing device, and a mounting unit disposed in the housing, the mounting unit receiving the semiconductor package, wherein a size of the mounting unit corresponds to a size of a ball area of the semiconductor package.

Abstract: A semiconductor memory device and its operating method are disclosed. The semiconductor memory device includes; a memory cell array including a plurality of memory cells selected in relation to a plurality of word lines and a plurality of bit lines, an address decoder selecting at least one word line in response to a refresh address and selecting all of the plurality of bit lines in response to a hidden write signal when a CBR refresh operation is requested during a test mode, a hidden write control circuit generating the hidden write signal when the CBR refresh operation is requested during the test mode, a refresh address generating circuit generating the refresh address when the CBR refresh operation is requested during the test mode, and a data input circuit applying data to all of the plurality of bit lines when the CBR refresh operation is requested during the test mode.

Abstract: An integrated circuit apparatus including an improved test circuit and a method of testing the integrated circuit apparatus are provided. The integrated circuit apparatus determines pass or fail of the integrated circuit apparatus itself by comparing internal DQ data output by a core logic circuit with test patterns set by a mode register set (MRS) code or test patterns directly input from an external source.

Abstract: A socket for testing a semiconductor package comprises two or more rubbers. Each rubber includes a chip-package contact portion configured to electrically connect with a chip package placed on the rubber and electrical wirings configured to electrically connect with the chip-package contact portion and having external contact ends configured to electrically connect with external electrical connections. The socket also comprises two or more guides configured to receive the chip package therein, the two or more guides including electrical wirings having external contact ends that are configured to be electrically connected with external electrical connections and a socket frame configured to hold the two or more rubbers and the two or more guides, wherein the rubbers correspond in number to the guides, and the rubbers and the guides are alternately stacked so that one rubber is located at a lowermost portion in a holding space of the socket frame.

Abstract: A semiconductor memory device and its operating method are disclosed. The semiconductor memory device includes; a memory cell array including a plurality of memory cells selected in relation to a plurality of word lines and a plurality of bit lines, an address decoder selecting at least one word line in response to a refresh address and selecting all of the plurality of bit lines in response to a hidden write signal when a CBR refresh operation is requested during a test mode, a hidden write control circuit generating the hidden write signal when the CBR refresh operation is requested during the test mode, a refresh address generating circuit generating the refresh address when the CBR refresh operation is requested during the test mode, and a data input circuit applying data to all of the plurality of bit lines when the CBR refresh operation is requested during the test mode.

Abstract: An integrated circuit apparatus including an improved test circuit and a method of testing the integrated circuit apparatus are provided. The integrated circuit apparatus determines pass or fail of the integrated circuit apparatus itself by comparing internal DQ data output by a core logic circuit with test patterns set by a mode register set (MRS) code or test patterns directly input from an external source.

Abstract: A test board is selectively usable as an interface between an integrated circuit device under test (DUT), such as a ball grid array package, and an automatic test equipment (ATE), and as an interface between a calibration apparatus and the ATE. The test board includes a socket, for electrically connecting to the ATE, which includes a plurality of contact terminals which are configured to directly contact terminals of the DUT during a test operation and to directly contact probes of the calibration apparatus during a calibration operation. The test board also includes an alignment mark which is positioned adjacent the socket and which can be sensed by the calibration apparatus during the calibration operation, and a test pad which is positioned adjacent the socket and which is configured to directly contact a test probe of the calibration apparatus for checking an operational state of the calibration apparatus.

Abstract: A test board is selectively usable as an interface between an integrated circuit device under test (DUT), such as a ball grid array package, and an automatic test equipment (ATE), and as an interface between a calibration apparatus and the ATE. The test board includes a socket, for electrically connecting to the ATE, which includes a plurality of contact terminals which are configured to directly contact terminals of the DUT during a test operation and to directly contact probes of the calibration apparatus during a calibration operation. The test board also includes an alignment mark which is positioned adjacent the socket and which can be sensed by the calibration apparatus during the calibration operation, and a test pad which is positioned adjacent the socket and which is configured to directly contact a test probe of the calibration apparatus for checking an operational state of the calibration apparatus.

Abstract: A package tape for testing a chip assembled by a packaging method such as a micro-ball grid array (BGA) package, whereby the chip is designed to face downward. The package tape includes one or more taps, disposed on a guard area other than an area where a semiconductor chip is attached, for testing the semiconductor chip. One or more pads are disposed on the area where the semiconductor chip is attached and are attached to corresponding test pads on the semiconductor chip. One or more leads which electrically connect the taps with the pads. The package tape advantageously enables easy testing of the electric characteristics of the semiconductor chip, which in a typical BGA package tape cannot be tested by probing since the circuit thereof faces down.

Abstract: A package tape for testing a chip assembled by a packaging method such as a micro-ball grid array (BGA) package, whereby the chip is designed to face downward. The package tape includes one or more taps, disposed on a guard area other than an area where a semiconductor chip is attached, for testing the semiconductor chip. One or more pads are disposed on the area where the semiconductor chip is attached and are attached to corresponding test pads on the semiconductor chip. One or more leads which electrically connect the taps with the pads. The package tape advantageously enables easy testing of the electric characteristics of the semiconductor chip, which in a typical BGA package tape cannot be tested by probing since the circuit thereof faces down.