Abstract: A method for converting an image resolution converts a low resolution image into a high resolution image, generates a second high resolution image by compensating an image quality of the high resolution image, and selectively compensating, by using information about a specific region included in the low resolution image, a region which is included in the second high resolution image and corresponds to the specific region.

Abstract: An image compression circuit includes an encoder configured to compress a current frame and to output current frame compressed data and a current frame bitstream; a decoder configured to decode the previous frame bitstream and to output previous frame compressed data; a frame memory controller configured to write the current frame bitstream to a frame memory and simultaneously read a previous frame bitstream from the frame memory; a dynamic capacitance compensation controller configured to output a previous frame reference value based on the current frame, the current frame compressed data, and the previous frame compressed data; and an overdrive circuit configured to generate a current overdriven frame including an overdrive pixel value for a current pixel based on a pixel value of the current pixel in the current frame and the previous frame reference value.

Abstract: A method for converting an image resolution converts a low resolution image into a high resolution image, generates a second high resolution image by compensating an image quality of the high resolution image, and selectively compensating, by using information about a specific region included in the low resolution image, a region which is included in the second high resolution image and corresponds to the specific region.

Abstract: A coding circuit of the present invention converts n-bit binary data word at a prescribed clock cycle (t) into to an m-trit ternary code word, where n and m are integers and n.gtoreq.m. The coding circuit includes an (x) number of storage elements or latches and a (y) number of coders, each storage element or latch receiving (m.div.x) bits of the binary data word at a clock cycle of (t.div.x). After a prescribed delay period, a corresponding storage element or latch outputs the sampled bits to a corresponding coder at an increasing or decreasing edge of the clock signal. Each coder codes the sampled bits to (m.div.y) ternary code. The each of the coders outputs (m.div.y) ternary code onto a corresponding signal line of a bus. Hence, the coding circuit outputs m-trit ternary code word onto the bus. An exemplary coding circuit is illustrated where n=8, m=6, t=25 MHz, x=2 and y=2, and D flip-flops are used for the storage elements and latches.