Patents by Inventor Yoon-ho Son
Yoon-ho Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11329053Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.Type: GrantFiled: January 12, 2021Date of Patent: May 10, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
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Publication number: 20210134809Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.Type: ApplicationFiled: January 12, 2021Publication date: May 6, 2021Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
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Patent number: 10957647Abstract: Integrated circuit (IC) devices are provided. An IC device includes a substrate including an active region. The IC device includes a bit line on the substrate. The IC device includes a direct contact connected between the active region and the bit line. The IC device includes a contact plug on the substrate. Moreover, the IC device includes a boron-containing insulating pattern between the contact plug and the direct contact.Type: GrantFiled: March 19, 2019Date of Patent: March 23, 2021Inventors: Dong-kak Lee, Yoon-ho Son, Mong-sup Lee, Wook-yeol Yi
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Patent number: 10916549Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.Type: GrantFiled: September 16, 2019Date of Patent: February 9, 2021Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
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Publication number: 20200051921Abstract: Integrated circuit (IC) devices are provided. An IC device includes a substrate including an active region. The IC device includes a bit line on the substrate. The IC device includes a direct contact connected between the active region and the bit line. The IC device includes a contact plug on the substrate. Moreover, the IC device includes a boron-containing insulating pattern between the contact plug and the direct contact.Type: ApplicationFiled: March 19, 2019Publication date: February 13, 2020Inventors: Dong-kak Lee, Yoon-ho Son, Mong-sup Lee, Wook-yeol Yi
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Publication number: 20200013782Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.Type: ApplicationFiled: September 16, 2019Publication date: January 9, 2020Inventors: Yoon Ho SON, Jae Uk SHIN, Yong Sun KO, Im Soo PARK, Sung Yoon CHUNG
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Patent number: 10418366Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.Type: GrantFiled: January 4, 2018Date of Patent: September 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
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Patent number: 10297495Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: GrantFiled: April 2, 2018Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
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Patent number: 10290537Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: GrantFiled: January 5, 2017Date of Patent: May 14, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
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Publication number: 20180342521Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.Type: ApplicationFiled: January 4, 2018Publication date: November 29, 2018Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
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Publication number: 20180226290Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing atType: ApplicationFiled: April 2, 2018Publication date: August 9, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Mong-sup LEE, Sang-jun LEE, Yoon-ho SON
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Publication number: 20170133262Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing atType: ApplicationFiled: January 5, 2017Publication date: May 11, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Mong-sup LEE, Sang-jun LEE, Yoon-ho SON
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Patent number: 9570316Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: GrantFiled: May 21, 2015Date of Patent: February 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
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Publication number: 20150340281Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.Type: ApplicationFiled: May 21, 2015Publication date: November 26, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mong-sup LEE, Sang-jun LEE, Yoon-ho SON
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Patent number: 8962455Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.Type: GrantFiled: June 18, 2013Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyun Choi, Jin-Ho Noh, Yoon-Ho Son, Dae-Hyuk Chung, In-Seak Hwang, Tae-Joon Park, Tae-Ho Hwang
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Patent number: 8723297Abstract: In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.Type: GrantFiled: July 7, 2011Date of Patent: May 13, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon-Ho Son, Mong-Sup Lee, In-Seak Hwang, Dae-Hyuk Chung, Suk-Hun Choi, Sang-Jun Lee
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Publication number: 20130341710Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.Type: ApplicationFiled: June 18, 2013Publication date: December 26, 2013Inventors: Sang-Hyun CHOI, Jin-Ho NOH, Yoon-Ho SON, Dae-Hyuk CHUNG, In-Seak HWANG, Tae-Joon PARK, Tae-Ho HWANG
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Patent number: 8357613Abstract: A method of fabricating a semiconductor device includes depositing tungsten on an insulating layer in which a contact hole is formed by chemical vapor deposition (CVD), performing chemical mechanical planarization (CMP) on the tungsten to expose the insulating layer and form a tungsten contact plug, and performing rapid thermal oxidation (RTO) on the tungsten contact plug in an oxygen atmosphere such that the tungsten expands volumetrically into tungsten oxide (W?O?).Type: GrantFiled: February 12, 2010Date of Patent: January 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Hun Choi, Chang-Ki Hong, Jae-Hyoung Choi, Yoon-Ho Son, Min-Young Park, Yong-Suk Tak
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Patent number: 8148710Abstract: A phase-change memory device including a first contact region and a second contact region formed on a semiconductor substrate. A first insulating layer with a first contact hole and a second contact hole is disposed on the semiconductor substrate, exposing the first and second contact regions. A first conductive layer is disposed on the first insulating interlayer to fill the first and the second contact holes. A first protection layer pattern and a lower wiring protection pattern are disposed on the first conductive layer. A first contact with a first electrode and a second contact with a lower wiring are disposed so as to connect the first and second contact regions. A second protection layer with a second electrode is disposed on the first protection layer pattern and the lower wiring protection pattern. A via filled with a phase-change material is disposed between the first electrode and the second electrode.Type: GrantFiled: August 20, 2010Date of Patent: April 3, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Suk-Hun Choi, Chang-Ki Hong, Yoon-Ho Son, Jang-Eun Heo
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Publication number: 20120025283Abstract: In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.Type: ApplicationFiled: July 7, 2011Publication date: February 2, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoon-Ho Son, Mong-Sup Lee, In-Seak Hwang, Dae-Hyuk Chung, Suk-Hun Choi, Sang-Jun Lee