Abstract: Internal phase shifting is achieved by adding a feedback divider to a feedback loop of a phase locked loop circuit configured to determine a transmission frequency of a wireless transmission terminal and adding a phase adjustment current to a loop current. Since the phase adjustment current is applied to an adder circuit, a phase difference is maintained even when the feedback loop is in a stable state, and accordingly, an output of the feedback divider maintains the phase difference with a reference frequency as intended by the phase adjustment current applied to the adder circuit.

Abstract: An RC-triggered electrostatic discharge (ESD) power clamp circuit and method for providing ESD protection uses a control circuit with a latch to selectively activate a clamping transistor to discharge ESD on a first voltage rail to a second voltage rail.

Abstract: An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device uses the thin-oxide N-LDD implantation, and thus its ESD robustness is enhanced. This is performed by updating the logic Boolean operations of thick gate-oxide and thin gate-oxide N-LDD before fabricating the masks. In TGO, the intermediate-oxide ESD uses thin-oxide N-LDD implantation, and the thick-oxide ESD uses intermediate-oxide N-LDD implantation.

Abstract: An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device uses the thin-oxide N-LDD implantation, and thus its ESD robustness is enhanced. This is performed by updating the logic Boolean operations of thick gate-oxide and thin gate-oxide N-LDD before fabricating the masks. In TGO, the intermediate-oxide ESD uses thin-oxide N-LDD implantation, and the thick-oxide ESD uses intermediate-oxide N-LDD implantation.

Abstract: A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.