Abstract: A novel antibacterial peptide or peptide analog and a therapeutic use thereof for bacterial infections are disclosed. Specifically, the peptide or peptide analog has a structure in which an amphipathic, alpha-helical peptide composed of hydrophobic amino acids and hydrophilic amino acids is kinked, with a fatty acid bound to the N-terminus thereof. The peptide or peptide analogs have a therapeutic use for bacterial infections, especially, infections caused by Gram-negative bacteria.

Abstract: A wafer level chip scale package having stud bumps and a method for fabricating the same are described. The wafer level chip scale package includes a silicon substrate having a passivation layer and a chip pad on its top surface; a stud bump being formed on the chip pad and encircled by a first insulating layer; a re-distributed line (RDL) pattern being formed on the same horizontal surface as the first insulating layer and the stud bump, the RDL pattern for connecting the stud bump and a solder bump; a second insulating layer for insulating the RDL pattern so that a portion of the RDL pattern that is connected with the solder bump is exposed; and the solder bump being attached to the exposed portion if the RDL pattern.

Abstract: A method is disclosed. The method includes forming a substrate with a leadframe and a molding compound. The molding compound fills internal spaces in the leadframe and forms a dam structure. An optical emitter and an optical receiver are placed on the substrate. An optically transmissive medium is formed between the optical emitter and optical receiver.

Abstract: Provided are a lead frame and a semiconductor package which allows reliable attachment of a small-sized semiconductor chip requiring a large number of leads to a board while providing high heat dissipation capability. The semiconductor package includes leads, each having a top plate extending inward from the outside edge of a frame and a plurality of pillar-shaped portions supporting the top plates, a semiconductor chip attached onto edge portions of the leads, wires connecting the leads with corresponding bonding pad on the semiconductor chip, and a molding material encapsulating the semiconductor chip and the wires and parts of the leads so as to the bottom surfaces of the leads are exposed. Further, some embodiments have a conductive pad exhibiting higher heat dissipation.

Abstract: A method is disclosed. The method includes forming a substrate with a leadframe and a molding compound. The molding compound fills internal spaces in the leadframe and forms a dam structure. An optical emitter and an optical receiver are placed on the substrate. An optically transmissive medium is formed between the optical emitter and optical receiver.

Abstract: Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.

Abstract: Provided are a lead frame and a semiconductor package which allows reliable attachment of a small-sized semiconductor chip requiring a large number of leads to a board while providing high heat dissipation capability. The semiconductor package includes leads, each having a top plate extending inward from the outside edge of a frame and a plurality of pillar-shaped portions supporting the top plates, a semiconductor chip attached onto edge portions of the leads, wires connecting the leads with corresponding bonding pad on the semiconductor chip, and a molding material encapsulating the semiconductor chip and the wires and parts of the leads so as to the bottom surfaces of the leads are exposed. Further, some embodiments have a conductive pad exhibiting higher heat dissipation.

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing no UBM between a chip pad and an RDL pattern is described. As well, the device contains only a single non-polymeric insulation layer between the RDL pattern and the solder bump. The single non-polymeric insulation layer does not need high temperature curing processes and so does not induce thermal stresses into the device. As well, manufacturing costs are diminished by eliminating the UBM between the chip pad and the RDL pattern.

Abstract: Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing an adhesive film containing conductive particles sandwiched between a chip with Cu-based stud bumps and a substrate containing a bond pad. Some conductive particles are sandwiched between the stud bump and bond pad to create a conductive path. The wafer level chip scale package is manufactured without the steps of dispensing solder and reflowing the solder and can optionally eliminate the use of a redistribution trace. Using such a configuration increases the reliability of the wafer-level chip scale package.

Abstract: The stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding-pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame by utilizing a conductive adhesive material. A connecting hole is formed in the outer end of the inner lead for better electrical connection when soldered. The entire resultant structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Abstract: A power semiconductor package is provided. The power semiconductor package includes a chip, leads, conductive media, and a molding material. The leads have a groove in the shape of a hemisphere or a down-set. The package further includes an adhesive. The package can increase solder joint reliability and thermal performance. Also, the size of the package can be reduced, and sawing can be performed so that a burr does not occur.

Abstract: A wafer level chip scale package having stud bumps and a method for fabricating the same are described. The wafer level chip scale package includes a silicon substrate having a passivation layer and a chip pad on its top surface; a stud bump being formed on the chip pad and encircled by a first insulating layer; a re-distributed line (RDL) pattern being formed on the same horizontal surface as the first insulating layer and the stud bump, the RDL pattern for connecting the stud bump and a solder bump; a second insulating layer for insulating the RDL pattern so that a portion of the RDL pattern that is connected with the solder bump is exposed; and the solder bump being attached to the exposed portion if the RDL pattern.

Abstract: A power semiconductor package is provided. The power semiconductor package includes a chip, leads, conductive media, and a molding material. The leads have a groove in the shape of a hemisphere or a down-set. The package further includes an adhesive. The package can increase solder joint reliability and thermal performance. Also, the size of the package can be reduced, and sawing can be performed so that a burr does not occur.

Abstract: The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame. The entire structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Abstract: The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame. The entire structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.

Abstract: The present invention discloses a chip scale package. According to this invention, a lead frame 130 is bonded with an adhesive 140 to a bottom face of a semiconductor chip 110. An inner lead 131 of the lead frame 130 is connected to a pad 111 of the semiconductor chip with a metal wire 120, and thickness of the inner lead 131 is equal to an original thickness of the lead frame 130. An outer lead 132 of the lead frame 130 is formed by partially etching a bottom face of the lead frame 130. The entire resultant is encapsulated with a molding compound 100 such that the outer lead 132 is exposed therefrom, especially there is formed a downward protruding portion 101 at the molding compound 100 in the lower inner lead portion 131. This protruding portion raises the margin controlling the bonding height during the wire-bonding process such that the metal wire 120 is not exposed from the molding compound 100.

Abstract: Disclosed is a stack package. In the stack package, at least two semiconductor chips 40 are disposed up and down. Inner leads 31 of lead frames 30 are attached at a bonding pad-disposed face of the semiconductor chip 40. The inner leads 31 are electrically connected to the bonding pads of the semiconductor chips 40 with metal wires 50. Protruding portions 33,34 are formed at the inner leads 31 toward downside and upside. To expose the respective protruding portions 33,34 and outer leads 32 formed at the lowermost lead frame 30, the respective semiconductor chips 40 are molded with an epoxy compound 60. The respective lead frames 30 are electrically connected by contacting the upwardly or downwardly protruding portions 34, 33 from the respective lead frames.