Patents by Inventor Yoon-Hwan SON
Yoon-Hwan SON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230337431Abstract: A semiconductor memory device and a method for fabricating a semiconductor memory device, the device including a peripheral logic structure on a substrate; a horizontal conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a plate contact plug connected to the horizontal conductive substrate; and a first penetration electrode connected to the lower connection wiring body, wherein upper surfaces of the plate contact plug and the first penetration electrode are on a same plane, the plate contact plug includes an upper part and a lower part directly connected to each other, the first penetration electrode includes an upper part and a lower part directly connected to each other, moving away from upper surfaces of the first penetration electrode and the plate contact plug, widths of the upper parts increase and widths of the lower parts decrease.Type: ApplicationFiled: June 22, 2023Publication date: October 19, 2023Inventors: Ga Eun Kim, Yoon Hwan Son, Sung Won Cho, Joo Hee Park
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Patent number: 11723202Abstract: A semiconductor memory device and a method for fabricating a semiconductor memory device, the device including a peripheral logic structure on a substrate; a horizontal conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a plate contact plug connected to the horizontal conductive substrate; and a first penetration electrode connected to the lower connection wiring body, wherein upper surfaces of the plate contact plug and the first penetration electrode are on a same plane, the plate contact plug includes an upper part and a lower part directly connected to each other, the first penetration electrode includes an upper part and a lower part directly connected to each other, moving away from upper surfaces of the first penetration electrode and the plate contact plug, widths of the upper parts increase and widths of the lower parts decrease.Type: GrantFiled: September 28, 2020Date of Patent: August 8, 2023Inventors: Ga Eun Kim, Yoon Hwan Son, Sung Won Cho, Joo Hee Park
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Patent number: 11195856Abstract: A semiconductor device includes a first substrate in which a first region and a second region are defined, a first stack structure with first gate electrodes displaced and stacked sequentially on the first substrate, a second stack structure with second gate electrodes displaced and stacked sequentially on the first stack structure, a junction layer disposed between the first stack structure and the second stack structure, a first interlayer insulating layer disposed on a side surface of the first stack structure, a second interlayer insulating layer covering the second stack structure, a first channel hole that penetrates through structure(s) and/or layer(s) and a second channel hole that penetrates through structure(s) and/or layer(s). A height of the second portion of the first channel hole in a second direction orthogonal to the first direction is less than a height of the second portion of the second channel hole in the second direction.Type: GrantFiled: February 26, 2020Date of Patent: December 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon Hwan Son, Ji Sung Cheon
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Publication number: 20210288068Abstract: A semiconductor memory device and a method for fabricating a semiconductor memory device, the device including a peripheral logic structure on a substrate; a horizontal conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a plate contact plug connected to the horizontal conductive substrate; and a first penetration electrode connected to the lower connection wiring body, wherein upper surfaces of the plate contact plug and the first penetration electrode are on a same plane, the plate contact plug includes an upper part and a lower part directly connected to each other, the first penetration electrode includes an upper part and a lower part directly connected to each other, moving away from upper surfaces of the first penetration electrode and the plate contact plug, widths of the upper parts increase and widths of the lower parts decrease.Type: ApplicationFiled: September 28, 2020Publication date: September 16, 2021Inventors: Ga Eun KIM, Yoon Hwan SON, Sung Won CHO, Joo Hee PARK
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Patent number: 10950624Abstract: A vertical memory device includes gate electrodes on a substrate and a channel. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes, and includes a first portion, a second portion and a third portion. The second portion is formed on and connected to the first portion, and has a sidewall slanted with respect to the upper surface of the substrate so as to have a width gradually decreasing from a bottom toward a top thereof. The third portion is formed on and connected to the second portion.Type: GrantFiled: May 22, 2019Date of Patent: March 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Cheon Baek, Ji-Ye Noh, Yoon-Hwan Son, Ji-Sung Cheon
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Patent number: 10930664Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.Type: GrantFiled: June 27, 2019Date of Patent: February 23, 2021Inventors: Yoon Hwan Son, Seok Cheon Baek, Ji Sung Cheon
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Publication number: 20200395378Abstract: A semiconductor device includes a first substrate in which a first region and a second region are defined, a first stack structure with first gate electrodes displaced and stacked sequentially on the first substrate, a second stack structure with second gate electrodes displaced and stacked sequentially on the first stack structure, a junction layer disposed between the first stack structure and the second stack structure, a first interlayer insulating layer disposed on a side surface of the first stack structure, a second interlayer insulating layer covering the second stack structure, a first channel hole that penetrates through structure(s) and/or layer(s) and a second channel hole that penetrates through structure(s) and/or layer(s). A height of the second portion of the first channel hole in a second direction orthogonal to the first direction is less than a height of the second portion of the second channel hole in the second direction.Type: ApplicationFiled: February 26, 2020Publication date: December 17, 2020Inventors: YOON HWAN SON, JI SUNG CHEON
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Patent number: 10825934Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: GrantFiled: January 6, 2020Date of Patent: November 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
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Patent number: 10777577Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connecting region; a stacked structure including a lower stacked structure and an upper stacked structure sequentially stacked on a substrate, wherein the stacked structure includes an insulating layer and electrodes alternately stacked vertically on the substrate; a vertical structure in a channel hole passing through the lower stacked structure and the upper stacked structure on the cell array region; and a dummy structure in a dummy hole passing through at least one of a lower stacked structure and an upper stacked structure on a connecting region. The connecting region includes a second connecting region on one side of the cell array region and a first connecting region on one side of the second connecting region. A surface pattern shape of the dummy hole in the second connecting region is different from a shape of the dummy hole in the first connecting region.Type: GrantFiled: July 2, 2019Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-sung Cheon, Seok-cheon Baek, Yoon-hwan Son, Jun-young Choi
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Publication number: 20200203367Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connecting region; a stacked structure including a lower stacked structure and an upper stacked structure sequentially stacked on a substrate, wherein the stacked structure includes an insulating layer and electrodes alternately stacked vertically on the substrate; a vertical structure in a channel hole passing through the lower stacked structure and the upper stacked structure on the cell array region; and a dummy structure in a dummy hole passing through at least one of a lower stacked structure and an upper stacked structure on a connecting region. The connecting region includes a second connecting region on one side of the cell array region and a first connecting region on one side of the second connecting region. A surface pattern shape of the dummy hole in the second connecting region is different from a shape of the dummy hole in the first connecting region.Type: ApplicationFiled: July 2, 2019Publication date: June 25, 2020Inventors: Ji-sung CHEON, Seok-cheon BAEK, Yoon-hwan SON, Jun-young CHOI
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Publication number: 20200185409Abstract: A vertical memory device includes gate electrodes on a substrate and a channel. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes, and includes a first portion, a second portion and a third portion. The second portion is formed on and connected to the first portion, and has a sidewall slanted with respect to the upper surface of the substrate so as to have a width gradually decreasing from a bottom toward a top thereof. The third portion is formed on and connected to the second portion.Type: ApplicationFiled: May 22, 2019Publication date: June 11, 2020Inventors: Seok-Cheon BAEK, Ji-Ye NOH, Yoon-Hwan SON, Ji-Sung CHEON
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Publication number: 20200185402Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.Type: ApplicationFiled: June 27, 2019Publication date: June 11, 2020Inventors: YOON HWAN SON, Seok Cheon Baek, Ji Sung Cheon
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Publication number: 20200144427Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: ApplicationFiled: January 6, 2020Publication date: May 7, 2020Inventors: JOON-YOUNG KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE
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Patent number: 10529865Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: GrantFiled: April 27, 2018Date of Patent: January 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joon-Young Kwon, Shin-Young Kim, Yoon-Hwan Son, Jae-Jung Lee, Joon-Sung Kim, Seung-Min Lee
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Publication number: 20190035942Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate.Type: ApplicationFiled: April 27, 2018Publication date: January 31, 2019Inventors: Joon-Young KWON, Shin-Young KIM, Yoon-Hwan SON, Jae-Jung LEE, Joon-Sung KIM, Seung-Min LEE