Abstract: Provided are a semiconductor memory device and a data write and read method thereof. The semiconductor memory device includes a write data controller, an address controller, and a read data controller. The write data controller writes data received with an address to a first memory cell corresponding to the address and simultaneously stores the data in a data register. The address controller decodes and stores the address in an address register. The read data controller outputs data from a second memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputs the data stored in the data register if the received address is equal to the address stored in the address register.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided in which sub-word line driver circuitry is designed with layout patterns that enable increased integration density and high performance operation.

Abstract: Provided are a semiconductor memory device and a data write and read method thereof. The semiconductor memory device includes a write data controller, an address controller, and a read data controller. The write data controller writes data received with an address to a first memory cell corresponding to the address and simultaneously stores the data in a data register. The address controller decodes and stores the address in an address register. The read data controller outputs data from a second memory cell corresponding to an address received with a data read command if the received address is different from the address stored in the address register, and outputs the data stored in the data register if the received address is equal to the address stored in the address register.