Patents by Inventor Yoon-Jay Cho

Yoon-Jay Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7319347
    Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: January 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Jay Cho, Il-Hun Son, Jae-Il Byeon
  • Patent number: 7304532
    Abstract: A voltage reference generator includes a current source for generating a source current in response to a control voltage and a current sink for conducting the source current to generate a reference voltage. Additionally, a switch block is configurable to determine the level of the source current conducted through the current sink. Furthermore, a reference current generator includes transistors operating in weak inversion with an active load coupled to one of the transistors.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: December 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-Jin Kim, Yoon-Jay Cho, Jeong-Seok Chae
  • Patent number: 7224198
    Abstract: An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: May 29, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Seok Chae, Yoon-Jay Cho, Hyo-Jin Kim
  • Publication number: 20060061413
    Abstract: A voltage reference generator includes a current source for generating a source current in response to a control voltage and a current sink for conducting the source current to generate a reference voltage. Additionally, a switch block is configurable to determine the level of the source current conducted through the current sink. Furthermore, a reference current generator includes transistors operating in weak inversion with an active load coupled to one of the transistors.
    Type: Application
    Filed: August 12, 2005
    Publication date: March 23, 2006
    Inventors: Hyo-Jin Kim, Yoon-Jay Cho, Jeong-Seok Chae
  • Publication number: 20060055376
    Abstract: An input and output circuit includes a common input and output node, an abnormal voltage detector and a clock generating circuit. The common input and output node is used as an output node in a normal operation mode and used as an input node in a test operation mode where an abnormal voltage level is inputted to the common input and output node. The abnormal voltage detector generates an abnormal voltage signal based upon a detection of the abnormal voltage level at the common input and output node in the test operation mode. The clock generating circuit outputs a first clock signal to the common input and output node in the normal operation mode and outputs a second clock signal to an external circuit in response to the abnormal voltage signal in the test operation mode. Therefore, time and expenses for testing the input and output circuit may be reduced.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 16, 2006
    Inventors: Jeong-Seok Chae, Yoon-Jay Cho, Hyo-Jin Kim
  • Publication number: 20050161733
    Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.
    Type: Application
    Filed: December 21, 2004
    Publication date: July 28, 2005
    Inventors: Yoon-Jay Cho, Il-Hun Son, Jae-Il Byeon