Patents by Inventor Yoon-Joo EOM

Yoon-Joo EOM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9355706
    Abstract: An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minsu Ahn, Seungjun Bae, Joon-Young Park, Yoon-Joo Eom
  • Publication number: 20160012879
    Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 14, 2016
    Inventors: Yoon-Joo EOM, JOON-YOUNG PARK, YONGCHEOL BAE, WON YOUNG LEE, SEONGJIN JANG, JUNGHWAN CHOI, JOOSUN CHOI
  • Patent number: 9209764
    Abstract: A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Chul Cho, Yong Cheol Bae, Yoon Joo Eom, Young Jin Jeon
  • Patent number: 9196325
    Abstract: An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Joo Eom, Byongmo Moon, Yongcheol Bae
  • Patent number: 9183902
    Abstract: An input data alignment circuit includes a data sampler, a frequency divider, a polarity determination block, and a data alignment block. The data sampler provides a data sequence based on data serially input according to a data strobe signal. The frequency divider generates a data alignment signal based on a divided frequency of the data strobe signal. The polarity determination block determines a polarity of the data alignment signal and provides a control signal based on the determined polarity. The data alignment block aligns the data sequence in parallel according to data alignment signal and control signal and generates output data.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-sik Moon, Seung-jun Bae, Joon-young Park, Yoon-joo Eom
  • Patent number: 9105317
    Abstract: Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Joo Eom, Young-Jin Jeon, Yong-Cheol Bae, Young-Chul Cho
  • Patent number: 9030262
    Abstract: An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Chul Cho, Yoon-Joo Eom, Young-Jin Jeon, Yong-Cheol Bae
  • Publication number: 20150063008
    Abstract: An input data alignment circuit includes a data sampler, a frequency divider, a polarity determination block, and a data alignment block. The data sampler provides a data sequence based on data serially input according to a data strobe signal. The frequency divider generates a data alignment signal based on a divided frequency of the data strobe signal. The polarity determination block determines a polarity of the data alignment signal and provides a control signal based on the determined polarity. The data alignment block aligns the data sequence in parallel according to data alignment signal and control signal and generates output data.
    Type: Application
    Filed: August 15, 2014
    Publication date: March 5, 2015
    Inventors: Dae-sik MOON, Seung-jun BAE, Joon-young PARK, Yoon-joo EOM
  • Publication number: 20150036448
    Abstract: An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.
    Type: Application
    Filed: July 2, 2014
    Publication date: February 5, 2015
    Inventors: MINSU AHN, SEUNGJUN BAE, JOON-YOUNG PARK, YOON-JOO EOM
  • Publication number: 20150023112
    Abstract: An integrated circuit includes a data input such as a data pad for receiving an external data signal input and an on-die termination (ODT) information input for receiving ODT information from an external device. An ODT circuit selectively couples a termination resistor to the data pad based on the ODT information. An input buffer is coupled to the data pad for determining data that is input into the pad using a reference voltage. A reference voltage generator is coupled to the input buffer and generates the reference voltage on the basis of the ODT information.
    Type: Application
    Filed: April 9, 2014
    Publication date: January 22, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Joo EOM, BYONGMO MOON, YONGCHEOL BAE
  • Patent number: 8934317
    Abstract: A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Jin Jeon, Yoon Joo Eom, Young Chul Cho
  • Publication number: 20130257534
    Abstract: An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 3, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Chul CHO, Yoon-Joo EOM, Young-Jin JEON, Yong-Cheol BAE
  • Publication number: 20130182513
    Abstract: Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
    Type: Application
    Filed: September 12, 2012
    Publication date: July 18, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoon-Joo EOM, Young-Jin JEON, Yong-Cheol BAE, Young-Chul CHO