Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

Abstract: A display device includes: a substrate including a display region including a plurality of pixel regions, and a non-display region at a periphery of the display region; a pixel circuit layer including a plurality of circuit elements in the display region; a display element layer including a plurality of light emitting devices in the display region on the pixel circuit layer; and first and second alignment lines in the non-display region, the first and second alignment lines each having a multi-layered structure. Each of the first and second alignment lines includes: a main line in a same layer as at least one electrode in the display element layer; and at least one sub-line electrically connected to the main line, the at least one sub-line in a same layer as at least one electrode in the pixel circuit layer.

Abstract: A pixel of an organic light emitting diode (OLED) display device may include an organic light-emitting diode; a first transistor configured to control, in response to a voltage of a first node, current flowing from a first driving power source to a second driving power source that is coupled to a second node via the organic light-emitting diode; a second transistor coupled between a data line and the first node, and configured to be turned on when a first scan signal is supplied to a first scan line; a storage capacitor coupled between the first node and the first driving power source; and an auxiliary capacitor coupled between the first driving power source and the second node.

Abstract: A display device includes: a substrate including a display region including a plurality of pixel regions, and a non-display region at a periphery of the display region; a pixel circuit layer including a plurality of circuit elements in the display region; a display element layer including a plurality of light emitting devices in the display region on the pixel circuit layer; and first and second alignment lines in the non-display region, the first and second alignment lines each having a multi-layered structure. Each of the first and second alignment lines includes: a main line in a same layer as at least one electrode in the display element layer; and at least one sub-line electrically connected to the main line, the at least one sub-line in a same layer as at least one electrode in the pixel circuit layer.

Abstract: A pixel of an organic light emitting diode (OLED) display device may include an organic light-emitting diode; a first transistor configured to control, in response to a voltage of a first node, current flowing from a first driving power source to a second driving power source that is coupled to a second node via the organic light-emitting diode; a second transistor coupled between a data line and the first node, and configured to be turned on when a first scan signal is supplied to a first scan line; a storage capacitor coupled between the first node and the first driving power source; and an auxiliary capacitor coupled between the first driving power source and the second node.