Patents by Inventor Yoon Min JO

Yoon Min JO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and light emitting element package including same
    Patent number: 12057537
    Abstract: Disclosed in an embodiment are a semiconductor device and a light-emitting device package including same, the semiconductor device comprising: a substrate; a plurality of semiconductor structures arranged in a matrix shape in the central area of the substrate; passivation layers arranged on upper surfaces and lateral surfaces of the semiconductor structures and on the edge area of the substrate; a plurality of first wiring lines which are arranged at lower parts of the plurality of semiconductor structures and electrically connected thereto, and which include first end parts extending from the central area to the edge area of the substrate; a plurality of second wiring lines which are arranged at the lower parts of the plurality of semiconductor structures and electrically connected thereto, and which include second end parts extending from the central area to the edge area of the substrate; a plurality of first pads penetrating the passivation layer so as to be connected to the plurality of first end parts;
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 6, 2024
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Sang Youl Lee, Ki Man Kang, Ji Hyung Moon, Yoon Min Jo
  • SEMICONDUCTOR DEVICE AND LIGHT EMITTING ELEMENT PACKAGE INCLUDING SAME
    Publication number: 20210066563
    Abstract: Disclosed in an embodiment are a semiconductor device and a light-emitting device package including same, the semiconductor device comprising: a substrate; a plurality of semiconductor structures arranged in a matrix shape in the central area of the substrate; passivation layers arranged on upper surfaces and lateral surfaces of the semiconductor structures and on the edge area of the substrate; a plurality of first wiring lines which are arranged at lower parts of the plurality of semiconductor structures and electrically connected thereto, and which include first end parts extending from the central area to the edge area of the substrate; a plurality of second wiring lines which are arranged at the lower parts of the plurality of semiconductor structures and electrically connected thereto, and which include second end parts extending from the central area to the edge area of the substrate; a plurality of first pads penetrating the passivation layer so as to be connected to the plurality of first end parts;
    Type: Application
    Filed: March 15, 2019
    Publication date: March 4, 2021
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Sang Youl LEE, Ki Man KANG, Ji Hyung MOON, Yoon Min JO