Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.

Abstract: A memory device may include: a memory bank comprising a first cell mat used as a normal area and a second cell mat used as a row hammer area and a redundancy area; a target address generation circuit suitable for: saving, in the row hammer area, a count of a received address for an active operation on the memory bank by performing an internal access operation on the row hammer area during the active operation, and setting, a particular count which satisfies a preset condition, an address corresponding to the particular count as a target address; a refresh control circuit suitable for controlling a smart refresh operation on the target address; and a column repair circuit suitable for repairing, when a bit line of the normal area has a defect, the bit line of the normal area with a bit line of the redundancy area.

Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.

Abstract: A method for operating a memory includes: receiving an active command and a row address; confirming that a portion of columns of a first row corresponding to the row address is replaced with a portion of columns of a second row; activating the first row and the second row; confirming activation of a random pulse; randomly selecting one among the row address corresponding to the first row and a row address corresponding to the second row in response to the activation of the random pulse; and sampling the selected row address as a sampling address.

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

Abstract: A memory system includes a plurality of memories, each including a plurality of data input terminals; and a memory controller configured to continuously transfer a first codeword and a second codeword to the data input terminals of the memories during a write operation.

Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.

Abstract: A memory device may include: a memory bank comprising a plurality of memory blocks, each divided into a normal area and a row hammer area, a command control circuit suitable for performing an access operation on the normal area in response to an active command, an internal command generation circuit suitable for generating an internal command in response to a precharge command, a target address generation circuit suitable for saving a count for each logic level combination of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and setting an address corresponding to the count as a target address when the count satisfies a preset condition, and a refresh control circuit suitable for controlling a smart refresh operation on the target address.

Abstract: A memory device may include: a memory bank comprising a first cell mat used as a normal area and a second cell mat used as a row hammer area and a redundancy area; a target address generation circuit suitable for: saving, in the row hammer area, a count of a received address for an active operation on the memory bank by performing an internal access operation on the row hammer area during the active operation, and setting, a particular count which satisfies a preset condition, an address corresponding to the particular count as a target address; a refresh control circuit suitable for controlling a smart refresh operation on the target address; and a column repair circuit suitable for repairing, when a bit line of the normal area has a defect, the bit line of the normal area with a bit line of the redundancy area.

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

Abstract: A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch.

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.

Abstract: A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch.

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.

Abstract: A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of mats connected to a word line. The column decoder includes a first repair circuit in which a first repair column address is stored, and a second repair circuit in which a second repair column address is stored. When the first repair column address coincides with a column address received in a read command or a write command, the column decoder selects other bit lines instead of bit lines corresponding to the received column address in one mat from among the plurality of mats. When the second repair column address coincides with the received column address, the column decoder selects other bit lines instead of the bit lines corresponding to the received column address in the plurality of mats.