Abstract: The method for preventing or treating of cancer includes administering a pharmaceutical composition to a subject in need thereof comprising a compound represented by Chemical Formula 1 below or a pharmaceutically acceptable salt thereof as an active ingredient. wherein the composition inhibits the growth of cancer cells.

Abstract: A method of processing a substrate includes attaching a first surface of a planarization film to a processing target substrate, disposing an electrostatic carrier onto a second surface opposite the first surface of the planarization film, fixing the processing target substrate to the electrostatic carrier by supplying power to the electrostatic carrier, and performing processing on the processing target substrate.

Abstract: The present invention relates to an improved method for synthesizing meropenem trihydrate[(1R,5S,6S)-2-[((2?S,4?S)-2?-dimethylaminocarbozyl)pyrrolidin-4?-ylthio]-6-[(R)-1-hydroxyethyl]-1-methylcarbapen-2-em-3-carboxylic acid, trihydrate], which is a novel carbapenem antibiotic.

Abstract: Provided are a system and method for manufacturing a semiconductor package. The system includes: a laser marker configured to irradiate a first laser beam on a strip to make a mark on the strip; and a laser saw configured to irradiate a second laser beam on the strip to cut the strip into individual semiconductor packages.

Abstract: The present invention relates to an improved method for synthesizing meropenem trihydrate [(1R,5S,6S)-2-[((2?S,4?S)-2?-dimethylaminocarbozyl)pyrrolidin-4?-ylthio]-6-[(R)-1-hydroxyethyl]-1-methylcarbapen-2-em-3-carboxylic acid, trihydrate], which is a novel carbapenem antibiotic.

Abstract: The present invention relates to a new, simple, and easy process for preparing cephalosporin antibiotics of the following formula (I), such as ceftazidime and cefixime. The process comprises acylating a 7-amino cephalosporanic acid derivative of the following formula (III) with a crystalline aminothiazole compound of the following formula (II): wherein R1 and R2 are the same or different and independently represent H, a C1-4 alkyl or C3-5 cycloalkyl group, R4 represents acetoxymethyl, methylpyridine, or vinyl, X represents chlorine or bromine, and the acid in the acid addition salt represents an inorganic acid, such as hydrochloric acid, or an organic acid, such as formic acid or acetic acid.

Abstract: The present invention relates to a new, simple, and easy process for preparing cephalosporin antibiotics of the following sub-formulas (I), such as cefixime.

Abstract: The present invention relates to a new crystalline aminothiazole derivative represented by the following formula (I) which is very useful for the preparation of cephalosporin antibiotics, including ceftazidime and cefixime, etc: wherein R1 and R2 are the same or different and independently represent H, an alkyl group of 1 to 4 carbon atoms, or a cycloalkyl group of 3 to 5 carbon atoms, X represents chlorine or bromine, and the acid in the acid addition salt represents an inorganic acid, such as hydrochloric acid, hydrobromic acid, sulfuric acid, or perchloric acid, or an organic acid, such as formic acid, acetic acid, trifluoroacetic acid, propionic acid, methanesulfonic acid, or benzenesulfonic acid.

Abstract: The present invention relates to an apparatus and a method for converting the binary floating point number into a integer represented as binary numbers of fixed length, the method for converting the binary floating point number into a integer comprising: calculating an exponent difference between the floating point number as a first operand and a constant which has a fraction of `0` value and an exponent of `data sizes of the integer-1` value as a second operand, shifting the fraction of the operand having the smaller exponent as many as the exponent difference, and outputting a bigger exponent; adding the fraction of the operand having the bigger exponent and a selected fraction, wherein the a selected fraction is in case of a negative value, the shifted fraction which is complemented to one, in case of a positive value, the shifted fraction itself in response to a sign of the first operand; and outputting the bigger exponent as a final result of the exponent, outputting and rounding the added fraction in re

Abstract: The present invention provides a method and an apparatus for performing multiply operation of floating point data in 2-cycle pipeline scheme, which can be applied to pipelined data path so that it is always capable of processing floating point data as long as the data is not contiguous, for reducing the area of the multiplier by reducing the number of basic cells used to 1/3 of that of basic cells used in conventional techniques.

Abstract: A clock circuit is used in a semiconductor device having a control block and a macroblock in order to provide synchronous clocks. The clock circuit contains a clock source for generating the clocks; a clock tree, coupled between the clock source and the control block and the macroblock, for relaying the clocks to the control block and the macrobock; and programmable delays coupled between the clock source and the clock tree and between the clock tree and the control block and the macroblock in order to reduce overall clock skew.

Abstract: An apparatus having a stack-top updating unit for processing an exchange instruction and a load instruction in parallel in a pipe-lined processor having a stack register file. Based on an information signal representing a modification of the stack-top after the current instruction is executed in a first pipe-line, a control signal indicating that a load instruction is executed by one of the first and second pipe-lines, and a second pipe-line enable signal, the stack-top updating unit generates a new stack-top signal and a current stack-top signal. The first pipe-line, in response to the current stack-top signal and operands, executes the operands, and the second pipe-line, in response to the new stack-top signal and the control signal, performs the load instruction or an exchange instruction. As a result, the load instruction or the Fload instruction can be simultaneously executed with another instruction or operand in the pipe-lined processor in an effective manner.

Abstract: This invention provides a clock generating apparatus that can control a skew between two-phase non-overlapping clocks in order to maintain constant non-overlapping period through an accurate analysis for the clock skew by a simple programming of delay. The invention has a delay block that receives first and second clock signals as inputs, and outputs them with delay. The invention also can control every skew in the chip and non-overlapping period of the first and the second clock signal by constituting the delay block being programmable.

Abstract: The present invention relates to an apparatus for sequentially controlling power to operate an LCD module through the internal circuit of an LCD controller, and comprises a timing and comparing means for receiving a timer value and a clock signal from an external circuit and outputting a match signal to control a time interval to sequentially generate said enable signals and to sequentially disable said enable signals; a display control means for controlling said display responsive to a display control signal, a write control signal and a reset signal from said external circuit; a power sequence FSM (finite state machine) for receiving the output of said display control means, said match signal from said timing and comparing means, said clock signal from an external circuit and a FSM reset signal, and outputting a clear signal to said timing and comparing means or outputting a first and second power enable signals and a control enable signal to said display; and a FSM reset signal generating means for receivi