Abstract: Provided is a method in an electricity-driven apparatus to be driven by receiving power through a plurality of battery packs in a parallel type. The method includes detecting a state of charge (SOC) of each of the plurality of battery packs, calculating a voltage difference between the plurality of battery packs based on the detected SOC, and performing battery pack balancing based on the calculated voltage difference exceeding a threshold value. The battery pack balancing is performed by a pre-charging circuit including a balancing relay.

Abstract: The present disclosure relates to a flight control apparatus, a system including the same, and a method thereof. An example embodiment of the present disclosure provides a flight control apparatus, including: at least one processor, and memory storing instructions that, when executed by the at least one processor, cause the flight control apparatus to determine, based on environmental information and based on variations of a parameter for each operation mode of an aerial vehicle, a flight path among at least one candidate path associated with a destination for the aerial vehicle.

Abstract: The present disclosure relates to a battery pack diagnosis control apparatus, a battery system including the same, and a method thereof. An exemplary embodiment of the present disclosure provides a battery system including: at least one battery pack; a flight control apparatus configured to transmit at least one of a battery discharge mode command or a motor discharge command; a battery control apparatus configured to transmit a relay control command for a relay based on receiving the battery discharge mode command, and transmit a diagnosis command based on receiving the motor discharge command; and at least one battery pack control apparatus configured to control the relay based on receiving the relay control command, and diagnose a failure of the at least one battery pack by measuring a current of the at least one battery pack based on receiving the diagnosis command.

Abstract: Systems and methods for soliton microcomb-based precision dimensional metrology via spectrally-resolved interferometry are described. In an embodiment, the system includes a dual-pumped soliton microcomb generator comprising a pump, a microresonator, and an auxiliary pump and that generates a single-soliton microcomb, an erbium-doped fiber amplifier that amplifies a C-band section of the soliton microcomb and a non-polarizing beam splitter that divides the soliton microcomb pulses into a reference arm pulse and a measurement arm pulse for an interferometer and recombines the reference arm pulse and the measurement arm pulse into a recombined beam upon their return.

Abstract: A method of controlling an active seatbelt includes checking whether a seatbelt is fastened, collecting driving information from a sensor or driving assist/safety system installed in a vehicle, determining a safety state of the vehicle based on the driving information, checking whether an airbag is deployed, and outputting a motor control signal for restraint control of the seatbelt in response to the safety state when the airbag is not deployed.

Abstract: A method of controlling an active seatbelt includes checking whether a seatbelt is fastened, collecting driving information from a sensor or driving assist/safety system installed in a vehicle, determining a safety state of the vehicle based on the driving information, checking whether an airbag is deployed, and outputting a motor control signal for restraint control of the seatbelt in response to the safety state when the airbag is not deployed.

Abstract: An active seat belt control apparatus is controlled according to a state of a vehicle. A control method for the active seat belt control apparatus includes: collecting, by a communication unit, state information about the vehicle; determining, by a controller, whether to activate a pulling operation of a seat belt using the collected state information; and activating the pulling operation of the seat belt using a motor.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The method includes applying a reference voltage to an unselected drain select line, applying a drain selection voltage to a selected drain select line, and applying a word line voltage to a normal word line. Before the word line voltage is applied to the normal word line, a positive voltage is applied to a dummy word line to bounce the unselected drain select line.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.

Abstract: A semiconductor memory device is operated by forming channels in a cell string including a plurality of memory cells and coupled between a bit line and a source line, applying first and second erase voltages having different levels to the channels through the bit line and the source line, respectively, and applying a first word line voltage to at least one word line among word lines coupled to the plurality of memory cells.

Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The method includes applying a reference voltage to an unselected drain select line, applying a drain selection voltage to a selected drain select line, and applying a word line voltage to a normal word line. Before the word line voltage is applied to the normal word line, a positive voltage is applied to a dummy word line to bounce the unselected drain select line.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array including memory blocks, a voltage generator configured to generate a precharge voltage; and a read and write circuit coupled to the memory blocks through bit lines, and configured to supply the precharge voltage to the bit lines when a selected memory block is accessed. Here, the precharge voltage varies depending on a distance between the read and write circuit and the selected memory block.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.

Abstract: A semiconductor memory device is operated by forming channels in a cell string including a plurality of memory cells and coupled between a bit line and a source line, applying first and second erase voltages having different levels to the channels through the bit line and the source line, respectively, and applying a first word line voltage to at least one word line among word lines coupled to the plurality of memory cells.

Abstract: A method for testing a memory cell of the semiconductor device includes the steps of determining a reference memory cell and setting a first trip point by measuring a first drain current of a reference memory cell, testing an erasure verifying memory cell to be tested at a room temperature, detecting a fourth drain current by measuring the erasure verifying memory cell at a hot temperature and comparing the fourth drain current with the first drain current, varying the first drain trip point according to a current difference between the firs and the fourth drain currents and setting a second trip point of the erasure verifying memory cell according to the varied first trip point.

Abstract: A method for testing a memory cell of the semiconductor device includes the steps of determining a reference memory cell and setting a first trip point by measuring a first drain current of a reference memory cell, testing an erasure verifying memory cell to be tested at a room temperature, detecting a fourth drain current by measuring the erasure verifying memory cell at a hot temperature and comparing the fourth drain current with the first drain current, varying the first drain trip point according to a current difference between the firs and the fourth drain currents and setting a second trip point of the erasure verifying memory cell according to the varied first trip point.